Transistor Simulation Parameter Calibration
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Solution Overview
Problem
Advanced circuit technologies, such as GAAFETs, require computationally intensive simulation processes for transistor design, which are time-consuming and resource-intensive, limiting their practical application in semiconductor manufacturing due to long turn-around times and high processing demands.
Innovation Solution
A circuit design process using simpler physical models that simulate carrier transport by solving drift-diffusion equations, calibrating model parameters to reduce processing time and resources while maintaining accuracy, allowing for efficient simulation of GAAFET designs across varying dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If computationally intensive simulation processes are used for transistor design, then simulation accuracy is improved, but processing time and computational resources increase significantly
Solution Approach 1:
The patent changes the physical model parameters from complex quantum mechanical models to simplified drift-diffusion models with calibrated parameters. This parameter transformation enables accurate simulation of carrier transport in GAAFET channels while dramatically reducing computational complexity and processing time requirements.
Solution Approach 2:
The patent creates a simplified computational model that copies the essential physical behavior of carrier transport without replicating the full complexity of quantum mechanical simulations. The drift-diffusion model with calibrated parameters reproduces key transport characteristics while using fraction of the computational resources.
2Measurement precision
If computationally intensive simulation processes are used for transistor design, then simulation accuracy is improved, but computational resources and processing demands increase
Solution Approach 1:
The patent transforms the simulation approach by changing from quantum mechanical parameter calculations to drift-diffusion parameter models. This parameter change maintains simulation accuracy for carrier transport characteristics while reducing computational resource consumption to manageable levels for standard processing systems.
Solution Approach 2:
The patent replaces complex quantum mechanical calculations with classical drift-diffusion equations. This substitution eliminates the need for intensive computational resources while preserving the essential physics of carrier transport in the transistor channel.
3Productivity
If simpler physical models are used for simulation, then processing time and resources are reduced, but simulation accuracy may deteriorate
Solution Approach 1:
The patent employs calibration processes that use experimental data or high-accuracy reference simulations to feedback-adjust the drift-diffusion model parameters. This feedback mechanism ensures that the simplified model maintains high accuracy in predicting carrier transport behavior while achieving fast simulation times.
Solution Approach 2:
The patent carefully selects and calibrates specific parameters in the drift-diffusion model to capture the essential physics of carrier transport. By changing the model parameters through calibration rather than using full quantum mechanical calculations, the patent achieves both speed and accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces computation resources and time required for transistor design simulations, improving design turn-around-time and accuracy, enabling faster and more efficient semiconductor manufacturing processes.
Implementation Method 1
A circuit design process using simpler physical models that simulate carrier transport by solving drift-diffusion equations
Data Source
AI summary
A system and method generates a model for a transistor design and simulates a transistor design using the model. A two-dimensional model of a transistor design is obtained. A density-gradient model for a channel of the transistor design is determined based on the two-dimensional model to generate a first set of parameters. A long-channel mobility model for the channel of the transistor design is determined based on the two-dimensional model to generate a second set of parameters. Further, a ballistic model and high-field saturation model of the transistor design are determined based on the first set of parameters and the second set of parameters to generate a third set of parameters. The third set of parameters are output to a memory device.