3D Transistor Structure with Single Deposition Gate and Shield
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Solution Overview
Problem
Transistors face challenges in increasing power density while maintaining device breakdown voltage and effective heat removal, which limits their performance and efficiency in various applications.
Innovation Solution
The development of a transistor structure with a common drain region and multiple source regions, coupled with a trench and tub region design, enhances current density and voltage breakdown by optimizing the doping profiles and dielectric layers to reduce on-resistance and parasitics, allowing for higher packing density and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the physical size of the die is reduced to increase power density, then device performance and packing density improve, but device breakdown voltage and heat removal capability deteriorate
Solution Approach 1:
The patent transitions from planar device structures to three-dimensional vertically-aligned structures. Multiple source regions are positioned at different vertical levels within a single die footprint, enabling increased power density without reducing the horizontal device dimensions that determine breakdown voltage and heat removal capability.
Solution Approach 2:
The patent implements nested source regions where multiple source structures are contained within overlapping horizontal footprints but separated vertically. This nesting allows multiple active regions to occupy the same planar space at different depths, increasing packing density while preserving the overall device envelope for voltage and thermal management.
2Manufacturing precision
If multiple deposition steps are used to form conductive layers, then layer precision and control improve, but manufacturing complexity and process time increase
Solution Approach 1:
The patent combines multiple conductive layer depositions into a single continuous deposition process. The conductive material is deposited across the entire wafer in one operation, forming all necessary conductive regions simultaneously, thereby reducing process steps while maintaining layer uniformity and precision.
Solution Approach 2:
The single deposition process serves multiple functions: it forms conductive layers for different source regions, creates interconnect structures, and establishes electrical pathways throughout the device. This multi-functional approach eliminates the need for separate deposition steps for each conductive feature.
Data Source
AI summary
A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.