Transistor Spacer With Concave Sidewall Reduces Leakage
Solution Overview
Problem
As semiconductor devices are miniaturized, they experience increased gate-induced drain leakage (GIDL) and hot carrier effects due to reduced gate thickness and spacer width, leading to performance issues, which conventional methods attempt to address by increasing source/drain implantation dosage but result in increased sheet resistance and gate-drain overlap capacitance.
Innovation Solution
A transistor design with a spacer having a concave outer surface is formed, where the spacer width is increased by forming a protrusive semiconductor portion with a leaned sidewall and a gate dielectric layer, allowing for self-aligned spacers that expand beyond the gate electrode, thereby reducing GIDL and hot carrier effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the semiconductor device is scaled down, then the device meets the trend of lighter, thinner, shorter and smaller products, but the gate thickness becomes less and the spacer width becomes shorter, resulting in high gate-induced drain leakage (GIDL) and severe hot carrier effect
Solution Approach 1:
The spacer structure is extended in the vertical dimension by forming a protrusive semiconductor portion that protrudes from the lower surface of the semiconductor substrate. This allows the spacer to have a greater effective width without increasing the planar footprint of the device, thus maintaining small device size while improving reliability by reducing GIDL and hot carrier effects through increased spacer width.
Solution Approach 2:
The protrusive semiconductor portion is formed in advance before the spacer formation process. This preliminary action creates a pre-formed structure that guides the subsequent spacer deposition, ensuring that the spacer automatically forms with increased width along the protrusive portion's sidewalls, thereby pre-positioning the structure to achieve the desired spacer width for reduced GIDL and hot carrier effects.
2Reliability
If the implanting dosage of source/drain extension (SDE) regions is increased to resolve GIDL and hot carrier effect, then these effects are alleviated, but the sheet resistance and gate-drain overlap capacitance are increased to affect the device performance
Solution Approach 1:
The increased spacer width is localized to specific regions where it is most needed for reducing GIDL and hot carrier effects, rather than uniformly increasing all device dimensions. The protrusive semiconductor portion creates localized spacer expansion that improves reliability without requiring global increases in device dimensions or implantation dosage that would adversely affect sheet resistance and capacitance.
3Reliability
If the spacer width is increased to alleviate GIDL and hot carrier effect, then these effects are reduced, but conventional methods increase sheet resistance and gate-drain overlap capacitance
Solution Approach 1:
The spacer width is increased by utilizing the vertical dimension through the protrusive semiconductor portion rather than increasing the planar dimensions. This dimensional approach allows the spacer to be wider in the vertical projection without increasing the horizontal device footprint, thereby reducing GIDL and hot carrier effects without introducing the sheet resistance and capacitance penalties associated with conventional planar scaling approaches.
Data Source
AI summary
A transistor and a method for forming the same are provided. The transistor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate includes a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.