Transistor Spacer Structure Blocking Etch Damage Paths
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Solution Overview
Problem
As semiconductor devices shrink in size, etch stop layers formed from deposited oxides fail to protect semiconductor nanostructures during polysilicon etching, leading to damage pathways and leakage between gate and source/drain regions, which can compromise device integrity.
Innovation Solution
A hard mask comprising a dielectric base material with a thin protective oxide surface is used to protect underlying nanostructures during etch processes, preventing damage to epitaxial source/drain regions and reducing leakage by controlling oxide thickness to avoid damage pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deposited oxide layers are used as etch stop layers, then etching can be performed, but the oxide layers fail to protect semiconductor nanostructures during polysilicon etching, leading to damage pathways and leakage
Solution Approach 1:
The protective structure is divided into multiple layers: a sacrificial oxide layer that is selectively removed to create the etch stop function, and a remaining protective layer that continues to shield the semiconductor nanostructures. This segmentation allows the etch stop layer to perform its function without compromising the protection of underlying structures.
Solution Approach 2:
The patent introduces an intermediary protective layer that mediates between the etchant and the semiconductor nanostructures. This intermediate layer is designed to be selectively removable, allowing it to serve as both a protective barrier during etching and a sacrificial element that can be removed to complete the device structure.
2Object-affected harmful factors
If oxide thickness is increased to provide better protection, then protection effectiveness improves, but damage pathways and leakage between gate and source/drain regions occur
Solution Approach 1:
The protective oxide structure is designed with non-uniform thickness and selective removal. The oxide layer is thickest where protection is most needed (over the semiconductor nanostructures) and is selectively removed in specific regions to prevent leakage pathways. This local quality variation allows simultaneous achievement of protection and leakage prevention.
Solution Approach 2:
The patent employs parameter changes in the oxide layer thickness and composition to optimize both protection and leakage prevention. By controlling the oxide thickness parameters and using selective removal processes, the structure achieves adequate protection while maintaining proper electrical isolation between gate and source/drain regions.
3Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but etch stop layers fail to protect nanostructures and damage pathways form
Solution Approach 1:
The protective oxide layer is formed preliminarily before the polysilicon etching process. This preliminary protective structure is in place to shield the scaled-down nanostructures from etchant damage during subsequent processing steps, enabling safe reduction of minimum feature size while maintaining reliability.
Solution Approach 2:
The patent uses composite material structures combining oxide layers with other materials that have different etch rates and protective properties. This composite approach allows the structure to provide protection during etching while being compatible with reduced feature sizes and preventing damage pathways in high-density integration scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hard mask effectively shields semiconductor layers from etchant damage, maintaining device integrity and reducing leakage, thereby enhancing the reliability of semiconductor devices.
Implementation Method 1
A hard mask comprising a dielectric base material with a thin protective oxide surface formed using an oxidation treatment... protects underlying nanostructures during etch processes
Implementation Method 2
a thin protective oxide surface formed using an oxidation treatment
Data Source
AI summary
A method of forming a semiconductor device that includes forming a hard mask layer on exterior surfaces of a stack of nanostructure layers, in which the hard mask layer including a dielectric base material and a protective oxide surface. A dummy gate is formed on the hard mask layer. A gate sidewall spacer is formed abutting the dummy gate. Source/drain regions are formed. The dummy gate is removed. A first set of the stack of nanostructure layers is removed selectively to a second set of the set of nanostructure layers. The second set of nanostructure layers provides suspended channel regions supported by an inner spacer. A damage path blocking portion of at least the dielectric base material of the hard mask layer is present between the inner spacer and the gate sidewall spacer.