Transistor Spacer Formation Without Feet or Active Layer Damage
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Solution Overview
Problem
Current methods for forming transistor spacers face challenges in achieving precise dimensional control and avoiding defects, particularly in FinFET and FDSOI transistors, where under-etching and over-etching lead to spacer feet and active layer damage, affecting transistor performance and reliability.
Innovation Solution
A method involving a two-layer dielectric structure where a first layer is anisotropically modified and a second layer is deposited and etched to form spacers without feet, ensuring precise control over spacer thickness and protecting the underlying active layer, using low-energy implantation and selective etching to minimize damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If anisotropic etching is used to form spacers, then spacer thickness control is improved, but spacer feet and active layer damage occur
Solution Approach 1:
The patent divides the spacer formation process into two distinct stages: first forming a mandrel structure with initial spacers, then removing the mandrel and forming final spacers. This segmentation allows each stage to be optimized independently, avoiding the trade-off between thickness control and damage prevention that plishes single-stage anisotropic etching
Solution Approach 2:
The patent performs preliminary actions by first forming the mandrel structure and initial spacers before final spacer formation. The initial spacers serve as templates that guide subsequent etching, ensuring precise dimensional control while the two-stage process prevents direct contact between aggressive etchants and the active layer
2Object-affected harmful factors
If low-energy plasma etching is used to reduce ion energy, then active layer damage is reduced, but etching anisotropy deteriorates
Solution Approach 1:
The patent segments the etching process into multiple steps with different conditions. The first etching step uses conditions optimized for anisotropy to form the mandrel, while subsequent steps use different parameters for spacer formation. This allows each step to be optimized for its specific purpose without compromise
Solution Approach 2:
The patent introduces intermediate structures (mandrel and initial spacers) that mediate between the deposition and final etching processes. These intermediaries protect the active layer from direct exposure to aggressive etchants while providing templates that ensure precise spacer dimensions through shadowing effects
3Manufacturing precision
If CF4/CH4 chemistry is used to improve Si3N4 etching selectivity, then etching selectivity is improved, but significant toe formation occurs
Solution Approach 1:
The patent segments the spacer formation into multiple stages, using different etching chemistries and parameters for each stage. The CF4/CH4 chemistry is used in controlled steps where toe formation is acceptable or can be corrected, while other chemistries are used in stages where precise profile control is critical
Solution Approach 2:
The patent dynamically adjusts etching parameters including chemistry composition, power, pressure, and temperature throughout the process. By varying these parameters between stages and even within steps, the process adapts to prevent toe formation in critical regions while maintaining high selectivity where needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of spacers with precise thickness and morphology, eliminating spacer feet and active layer defects, thereby improving transistor performance and reliability by maintaining the integrity of the active layer and reducing leakage currents.
Implementation Method 1
Perform anisotropic modification of the first layer along a preferred direction parallel to the lateral flanks of the grid pattern
Implementation Method 2
Deposit on the first layer a second layer of a second dielectric material
Implementation Method 3
Perform anisotropic etching of the second layer along a preferred direction parallel to the lateral flanks of the grid pattern
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 3
AI summary
According to one aspect, a process for forming spacers on a gate pattern is envisaged, comprising: - Deposition of a first dielectric layer including basal portions on the active layer and lateral portions on the flanks of the pattern, - Anisotropic modification of only the basal portions of this first layer, so as to obtain modified basal portions, - Deposition of a second dielectric layer on the first layer, also including basal and lateral portions, - Anisotropic etching of only the basal portions of this second layer, so as to eliminate these basal portions while retaining the lateral portions, - Removal of the modified basal portions while retaining the first and second unmodified lateral portions, by selective etching of the modified dielectric material relative to the unmodified dielectric material. - A preferred application area concerns the fabrication of FinFET or FDSOI transistors.