Transistor Stack Leakage Reduction via Threshold Voltage Variation
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in reducing power consumption due to body leakage and drain-to-source leakage in integrated circuits, particularly in system-on-chip devices with high and low voltage transistors, where existing hardware-based approaches increase circuit complexity and overhead.
Innovation Solution
A logic device configuration comprising a stack of transistors with varying threshold voltages, where P-channel transistors are coupled in parallel and N-channel transistors are connected in series, with at least one N-channel transistor having a first threshold voltage and another having a second threshold voltage, to minimize power consumption by optimizing leakage effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If hardware-based approaches are used to reduce body leakage, then power consumption is reduced, but circuit overhead and complexity increase
Solution Approach 1:
The patent changes the threshold voltage parameter of transistors by forming channels with different doping concentrations. High threshold voltage transistors are created by forming channels with lower doping concentrations, while low threshold voltage transistors use higher doping concentrations. This parameter change allows the same transistor structure to exhibit different leakage characteristics without adding hardware complexity.
Solution Approach 2:
The patent applies local quality by creating transistors with spatially varying doping concentrations within the semiconductor substrate. Different regions of the substrate have different doping levels, which locally adjust the threshold voltage of transistors formed in those regions. This allows selective reduction of body leakage in specific transistor instances without modifying the overall circuit architecture.
2Productivity
If transistor gate dimensions are reduced, then manufacturing cost decreases and performance improves, but body leakage effects increase
Solution Approach 1:
The patent compensates for increased body leakage in scaled transistors by changing the doping concentration parameter. As transistor dimensions are reduced, the doping concentration is adjusted to maintain optimal threshold voltage levels. This parameter adjustment counteracts the increased leakage effects that naturally occur with smaller gate dimensions.
Solution Approach 2:
The patent converts the harmful effect of increased body leakage in scaled transistors into a benefit by using the same scaling process to create regions with controlled doping concentrations. The miniaturization process itself is used to create the doping profiles needed to control leakage, turning the scaling-induced leakage problem into an opportunity for precise leakage management.
3Reliability
If multiple gate dielectric layers are formed, then transistor performance is improved, but re-growth of previous gate oxides occurs causing manufacturing defects
Solution Approach 1:
The patent extracts or removes the problematic first gate oxide layer before forming the second gate dielectric. By taking out the potentially defective first gate oxide through selective removal processes, the patent prevents re-growth issues when the second gate dielectric is formed, while still maintaining the benefits of multiple dielectric layers.
Solution Approach 2:
The patent performs preliminary actions by preparing the substrate and forming the first gate dielectric with controlled characteristics before forming the second gate dielectric. This preliminary formation establishes a foundation that prevents defects during subsequent processing, ensuring that the first gate oxide does not re-grow or interfere with the second layer formation.
Data Source
AI summary
Devices and methods are disclosed for logic gate devices to provide reduced leakage while improving performance. The device is configured for low leakage logic application where high threshold voltage devices are used to reduce leakage at the expense of reduced logic speed. Better performance is achieved than a high threshold voltage stack.