Transistor Stepped Profile Recess for Leakage Control
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Solution Overview
Problem
The increasing degree of integration in semiconductor memory devices, particularly in sub-100 nm channel structures, makes it difficult to achieve a desired threshold voltage, leading to issues such as increased leakage current and reduced data retention time when using conventional planar transistors, and fin field effect transistors exhibit challenges in memory devices due to triple channel formation.
Innovation Solution
A transistor structure that integrates a stepped profile and fin field effect transistor configurations, utilizing alternating trench device isolation layers and a recess region with a stepped profile, along with a gate stack overlapping the stepped profile and protruded portion, is manufactured using a damascene process to enhance operational characteristics and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar transistor structure is used, then the manufacturing process is simple, but the threshold voltage control becomes difficult in sub-100 nm channel structures
Solution Approach 1:
The patent transitions from a two-dimensional planar transistor structure to a three-dimensional structure by forming a recess region that extends vertically into the semiconductor substrate. This dimensional change allows the channel to have both lateral and vertical components, enabling better threshold voltage control through enhanced gate control over the channel region while maintaining compatibility with standard manufacturing processes.
2Productivity
If the degree of integration is increased, then the device density improves, but the short channel effect worsens and threshold voltage control becomes difficult
Solution Approach 1:
By forming a recess region that extends vertically into the substrate, the patent creates a three-dimensional channel structure that enhances gate control over the channel. This vertical dimension allows for better electrostatic control in highly integrated devices, mitigating short channel effects while maintaining high device density through efficient space utilization.
Solution Approach 2:
The recess region is formed within the active region of the semiconductor substrate, creating a nested structure where the channel is embedded in the substrate. This nesting approach allows for compact device layout and high integration density while maintaining effective gate control through the vertical recess structure.
3Power
If a fin field effect transistor is used, then the current drive ability improves, but the leakage current increases due to triple channel formation
Solution Approach 1:
The patent applies local quality by forming a recess region with specific geometric characteristics (depth, width, and shape) that are optimized for the channel region. The gate electrode is positioned to provide enhanced control specifically over the recessed channel portion, creating localized electric field distribution that improves current drive ability while suppressing leakage through precise spatial control of the electric field.
4Productivity
If a stepped profile structure is used, then the effective channel length increases while maintaining constant area, but the device complexity increases
Solution Approach 1:
The patent implements a stepped profile by forming the recess region with varying depths or widths at different lateral positions. This creates multiple channel segments with different effective lengths within a compact footprint, increasing the total effective channel length without proportionally increasing the device area. The manufacturing process uses standard etching and deposition techniques, keeping process complexity manageable.
Data Source
AI summary
A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.