Stress Analysis Method for Transistor Mobility Modeling
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Solution Overview
Problem
Current stress analysis methods for integrated circuit transistors, such as the LOD model, are limited in accounting for various stress sources and directions, leading to inaccurate modeling of carrier mobility and computation inefficiencies, making it impractical to analyze larger chip layouts.
Innovation Solution
A method that approximates stress in integrated circuit chip regions by considering multiple stress generation mechanisms, including STI-induced, silicon-germanium-induced, and strained cap layer stresses, and accounts for stress components in longitudinal, transverse, and vertical directions, using a sample point-based approach to estimate stress distribution and convert it into mobility enhancements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If 3-dimensional finite element analysis is used to model stress effects, then measurement precision of stress impact is improved, but computation time increases significantly
Solution Approach 1:
The patent segments the stress analysis into two distinct approaches: (1) 3-D finite element analysis for detailed accuracy-critical regions, and (2) a simplified analytical model for routine analysis of larger regions. This segmentation allows the system to obtain accurate results where needed without incurring the prohibitive computational cost of applying 3-D FEM to entire chips.
Solution Approach 2:
The patent applies partial action by using the simplified analytical model (which considers only the nearest STI interface) for the majority of transistors where high precision is not critical, and reserves the computationally intensive 3-D FEM analysis for specific regions where accurate stress modeling is essential. This selective application optimizes the balance between accuracy and computational efficiency.
2Productivity
If the simplified LOD model is used for stress analysis, then productivity is improved, but measurement precision of stress impact deteriorates
Solution Approach 1:
The patent segments transistors into two categories: those requiring simplified LOD model analysis (where speed is prioritized) and those requiring detailed 3-D FEM analysis (where precision is prioritized). This enables the system to maintain high productivity for routine analysis while ensuring precision for critical cases.
Solution Approach 2:
The patent applies the simplified LOD model partially - using it for transistors where approximate stress analysis suffices, while applying the more rigorous 3-D FEM method where precise stress modeling is necessary. This partial application of the simplified model maintains productivity without sacrificing required precision.
3Device complexity
If only the nearest STI interface is considered in stress modeling, then device complexity is reduced, but measurement precision of stress distribution deteriorates
Solution Approach 1:
The patent segments the stress sources into multiple categories: the nearest STI interface (handled by simplified model), and other stress sources including distant STI regions, silicon-germanium layers, and strained cap layers (handled by extended model). This segmentation allows the system to manage complexity while improving precision when needed.
Solution Approach 2:
The patent creates a universal stress analysis framework that can handle multiple stress sources (STI interfaces, silicon-germanium, strained cap layers) and can adapt its complexity level based on the specific analysis requirements, making the model versatile for different scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate stress analysis of larger regions, including entire integrated circuit chips, without the computational costs of 3-dimensional finite element analysis, allowing for improved transistor performance modeling and faster analysis of larger chip layouts.
Implementation Method 1
semiconductor materials such as silicon and germanium exhibit the piezoelectric effect (mechanical stress-induced changes in electrical resistance)
Implementation Method 2
During cooling, oxides tend to shrink less than the surrounding silicon, and therefore develop a state of compressive stress laterally on the silicon regions of the device
Data Source
AI summary
Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.