Transistor Breakdown Voltage via Sub-Amorphous Implantation
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Solution Overview
Problem
As low-voltage CMOS transistor technology scales, the breakdown voltages of high-voltage CMOS devices decrease due to abrupt PN junctions resulting from reduced gate length and poly gate thickness, limiting manufacturing processes and achieving insufficient breakdown voltages.
Innovation Solution
The method involves implanting atoms such as fluorine, silicon, or germanium into the substrate to create a sub-amorphous state, facilitating easier diffusion of dopants for source/drain region formation, thereby reducing the abruptness of the PN junction and increasing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low-voltage CMOS device technology scales down to reduce gate length, then device density and integration are improved, but breakdown voltage of high-voltage CMOS devices decreases due to abrupt PN junctions
Solution Approach 1:
The patent applies preliminary action by implanting atoms (fluorine, silicon, or germanium) into the substrate before forming the source/drain regions. This pre-treatment creates a sub-amorphous state in the silicon lattice that facilitates controlled dopant diffusion, allowing the formation of graded PN junctions that maintain high breakdown voltage even as device dimensions scale down for higher density.
2Adaptability or versatility
If poly gate thickness is reduced to match scaled low-voltage CMOS devices, then process compatibility is improved, but manufacturing precision for achieving effective anneal processes deteriorates
Solution Approach 1:
The patent changes the physical-chemical parameters of the substrate by introducing specific atoms (fluorine, silicon, or germanium) that alter the silicon lattice structure to a sub-amorphous state. This parameter change enables effective dopant diffusion and annealing processes even with reduced poly gate thickness, maintaining manufacturing precision while ensuring process compatibility across different device voltages.
3Reliability
If source/drain implant energy is reduced due to scaling, then low-voltage device performance is improved, but PN junction abruptness increases leading to higher electrical fields
Solution Approach 1:
The patent introduces atoms (fluorine, silicon, or germanium) as intermediaries in the source/drain region formation process. These intermediary atoms create a sub-amorphous state that acts as a diffusion facilitator, allowing dopants to distribute more uniformly and form graded junctions. This reduces the abruptness of the PN junction and lowers peak electrical fields while maintaining the low implant energies required for scaled low-voltage device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower electrical fields and higher breakdown voltages for high-voltage transistors, while maintaining minimal process complexity and not impacting other device performance, thus addressing the scaling challenges in CMOS device manufacturing.
Implementation Method 1
implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure
Implementation Method 2
implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate
Data Source
AI summary
The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.