Transistor Substrate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Emissive display devices face issues such as leakage current and luminance deterioration due to parasitic capacitance in transistors, which affect displaying quality, especially at high luminance and temperature.
Innovation Solution
A transistor substrate design is implemented with a semiconductor layer having specific channel and connecting portions, where the connecting portions have a narrower width than the channel portions, reducing parasitic capacitance by minimizing the overlapping area with signal lines, thereby stabilizing the gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the channel width is increased to improve current driving capability, then the transistor can drive higher luminance, but parasitic capacitance increases causing threshold voltage shift and leakage current
Solution Approach 1:
The channel is divided into two separate channel portions (first channel portion and second channel portion) connected by a connecting portion. This segmentation allows the channel to be optimized for both current driving capability and parasitic capacitance reduction, as each portion can be independently designed with appropriate width characteristics.
Solution Approach 2:
Different portions of the channel have different width characteristics: the first and second channel portions have a first width optimized for current driving, while the connecting portion has a second width (narrower than the first width) specifically optimized to reduce parasitic capacitance. This local differentiation resolves the contradiction between luminance driving capability and threshold voltage stability.
2Reliability
If the overlapping area with signal lines is increased to improve electrical connection, then signal transmission is enhanced, but parasitic capacitance increases causing leakage current and afterimages
Solution Approach 1:
The connecting portion is specifically designed with a narrower second width to minimize overlapping area with signal lines, thereby reducing parasitic capacitance. This local optimization allows the transistor to maintain reliable signal transmission while minimizing the harmful parasitic capacitance that causes leakage current and afterimages.
Solution Approach 2:
The connecting portion, which is necessary for electrical connection between channel portions, is designed with reduced width to convert the potential harm of overlapping with signal lines (parasitic capacitance) into a benefit (minimized parasitic capacitance). The narrower connecting portion maintains electrical connectivity while reducing the harmful capacitive coupling with adjacent signal lines.
3Illumination intensity
If the transistor operates at high temperature and high luminance, then display performance is improved, but leakage current and reliability deterioration increase
Solution Approach 1:
By segmenting the channel into multiple portions with different width characteristics, the transistor can operate at high luminance and temperature while maintaining reliability. The segmented structure distributes the electrical stress and reduces parasitic capacitance, preventing the reliability deterioration that typically occurs under high-temperature, high-luminance operating conditions.
Data Source
AI summary
A display device includes a substrate, a semiconductor layer disposed on the substrate, and including a first channel portion, a second channel portion, a connecting portion disposed between the first channel portion and the second channel portion, and electrode regions, a first insulating layer disposed on the semiconductor layer, a gate conductor disposed on the first insulating layer and including a first gate electrode overlapping the first channel portion and a second gate electrode overlapping the second channel portion, signal lines disposed on the substrate, a first electrode electrically connected to at least one of electrode regions of the semiconductor layer, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer, and the first channel portion and the second channel portion of the semiconductor layer each have a first width greater than a second width of the connecting portion.