Transistor Tip Profile via Selective Wet Etch
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Solution Overview
Problem
Silicon CMOS transistors face limitations in high-speed applications due to electron and hole mobility constraints, which are exacerbated by physical limitations and material properties, hindering their performance in high-frequency operations.
Innovation Solution
A method involving a wet etch technique to form source and drain regions with a highly faceted tip profile, using a selective etchant that preferentially etches the {111} crystallographic plane, resulting in improved carrier mobility, reduced contact resistance, and precise control of the metallurgical gate length, while minimizing contamination and surface non-uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dry etch techniques are used to form source and drain regions, then manufacturing process is simpler, but the tip profile exhibits bullet-shaped geometry with surface non-uniformity and contamination that degrades transistor performance
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary between the silicon substrate and the wet etch process. This oxide layer is selectively removed by the wet etchant to reveal the {111} crystallographic planes, which then guide the formation of the desired tip profile. The sacrificial layer mediates the interaction between the etch process and the crystal structure to achieve precise geometric control.
Solution Approach 2:
The invention changes the etching parameters by switching from dry etch to wet etch chemistry, and by controlling the etch selectivity to specific crystallographic planes. The wet etchant parameters are optimized to preferentially etch along {111} planes while leaving other orientations relatively intact, thereby transforming the tip geometry from bullet-shaped to highly faceted with improved uniformity.
2Productivity
If feature size is decreased to increase integration density, then device scaling is improved, but short channel effects and mobility limitations worsen transistor performance
Solution Approach 1:
The invention applies local quality by creating highly faceted tip profiles with specific crystallographic orientations at the source and drain regions. The {111} plane faceting is locally introduced at the tip regions where it most affects carrier transport, while the rest of the transistor structure maintains its conventional geometry. This localized structural modification improves carrier mobility and reduces short channel effects without requiring complete redesign of the entire device.
3Speed
If new materials and processing techniques are introduced to improve transistor performance, then switching speed and drive current increase, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The wet etch process with sacrificial oxide is a self-service technique where the process automatically reveals the desired {111} plane faceting through selective removal of the oxide layer. The crystallographic structure itself guides the etching process to form the correct geometry, reducing the need for additional alignment steps, masks, or complex process controls that would otherwise be required to achieve the same tip profile.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The wet etch technique enhances transistor performance by improving carrier mobility, reducing short channel effects, and decreasing contact resistance, enabling higher switching speeds and increased drive current with reduced power consumption.
Implementation Method 1
etching, with a TMAH or KOH wet etch, a source region and a drain region in the substrate, wet etch being selective to a crystallographic plane in the substrate and forming a facet in the {111} crystallographic plane
Implementation Method 2
The tips of the source and drain regions are formed by a wet etch and an epitaxial deposition
Data Source
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AI summary
Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.