High Voltage Transistor Vertical Drain Doping for Field Distribution
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Solution Overview
Problem
High voltage power transistors face challenges in achieving high breakdown voltage without increasing the length of the drift region, which affects their reliability and frequency operation characteristics due to concentrated electric fields and poor surface resistance distribution.
Innovation Solution
A high voltage power transistor design featuring a substrate with a P-type sub region, a well region, and a drain region with varying doping concentrations, including a highly doped N-type impurity region, an N-type impurity region, and a lightly doped P-type impurity region, along with conductive patterns for threshold voltage adjustment, to distribute electric fields and reduce hot carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length of the drift region is increased to provide high breakdown voltage, then the breakdown voltage is improved, but the horizontal area of the substrate is increased
Solution Approach 1:
The patent transitions from a planar drift region to a vertically structured drain region with multiple doped layers (highly doped N-type, lightly doped P-type, and P-type sub-region) stacked in the vertical dimension. This allows the breakdown voltage function to be achieved through vertical layering rather than horizontal extension, maintaining compact substrate area while achieving high voltage characteristics
Solution Approach 2:
The drain region is divided into distinct zones with different doping concentrations and types at different vertical positions: highly doped N-type impurity region at the top, lightly doped P-type impurity region in the middle, and P-type sub-region at the bottom. Each zone performs a specific function in managing electric fields and achieving breakdown voltage, allowing optimized local properties throughout the vertical structure
2Device complexity
If the electric fields are concentrated at the drain region sidewall, then the transistor structure is compact, but the breakdown voltage is lowered and reliability is poor
Solution Approach 1:
The patent systematically varies the doping concentration parameter through the vertical depth of the drain region, creating a gradient from highly doped N-type at the surface through lightly doped P-type in the middle to P-type sub-region at the bottom. This parameter change distributes the electric field intensity across different vertical zones, preventing concentration at any single location while maintaining the compact sidewall structure
3Reliability
If the surface resistance is low and bulk resistance is high, then the on currents flow along the surface, but the electric fields concentrate at the drain sidewall region
Solution Approach 1:
The lightly doped P-type impurity region acts as an intermediary layer between the highly doped N-type region (which carries the on-current) and the P-type sub-region (which provides bulk resistance). This intermediate layer with moderate doping concentration serves as a transition zone that manages the electric field distribution, preventing direct concentration at the drain sidewall while allowing surface current flow to continue
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances breakdown voltage reliability and high-frequency operation by decreasing electric field concentration and hot carrier injection, while maintaining a compact transistor structure.
Implementation Method 1
to distribute electric fields and reduce hot carrier injection
Implementation Method 2
decreasing electric field concentration and hot carrier injection
Data Source
AI summary
A transistor includes a substrate including a P-type-sub region doped with P-type impurities, a well region positioned at an upper portion of the substrate and doped with P-type impurities, a gate structure on the well region, and drain and source regions. The gate structure includes a gate insulation layer, first and second conductive patterns for adjusting a threshold voltage and a gate electrode. The drain and source regions are positioned at an upper portion of the substrate adjacent first and second sidewalk of the gate structure, respectively. The source region is doped with N-type impurities. The drain region includes a highly doped N-type impurity region, an N-type impurity region, and a lightly doped P-type impurity region sequentially disposed in a downward direction from a top surface of the substrate. A boundary between the well region and the P-type sub region is positioned under a bottom of the drain region.