Transistor Wiring Etching for Threshold Voltage Stability

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Solution Overview

Problem

Transistors with oxide semiconductors face challenges in maintaining high reliability and improved switching characteristics, particularly in long-term usage, due to shifts in threshold voltage during bias-thermal stress tests.

Innovation Solution

The method involves a two-step etching process for forming wiring layers with small taper angles, where the first etching has a higher rate for the conductive film than the semiconductor layer, and the second etching has higher rates for both the conductive film and semiconductor layer, ensuring improved coverage and reducing thickness unevenness, thereby enhancing the transistor's on-state current and maintaining a stable off-state current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single etching process is used to form wiring layers, then the manufacturing process is simple, but the coverage of layers is poor and thickness unevenness occurs

Engineering Contradiction:
Improveetching process simplicityVSAvoidlayer coverage and thickness uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The etching process is divided into two distinct steps: a first etching step that forms wiring layers with small taper angles, and a second etching step that further refines the structure. This segmentation allows each step to be optimized for specific purposes, improving overall manufacturing precision while maintaining reasonable process complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first etching step is performed as a preliminary action before the second etching step. By pre-forming the wiring layers with appropriate taper angles in the first step, the subsequent second etching step can focus on refining the structure, thereby achieving better coverage and thickness uniformity

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the etching rate for the conductive film is much higher than for the semiconductor layer, then the wiring layer formation is efficient, but the taper angle becomes large reducing coverage

Engineering Contradiction:
Improvewiring layer formation efficiencyVSAvoidtaper angle control and layer coverage
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is segmented into two steps with different rate characteristics. The first etching step uses conditions that provide moderate selectivity to achieve small taper angles, while the second step uses higher selectivity for refinement, thus balancing productivity and precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The etching parameters (gas composition, power, pressure) are changed between the two etching steps. The first step uses parameters optimized for small taper angle formation, while the second step uses parameters optimized for higher etching rates and better coverage, thus resolving the contradiction between efficiency and precision

Inventive Principle:
Principle #35Parameter changes

3Duration of action of stationary object

If the transistor operates for long term usage, then the device provides sustained functionality, but the threshold voltage shifts reducing reliability

Engineering Contradiction:
Improvetransistor operational lifespanVSAvoidthreshold voltage stability
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The two-step etching process is performed as a preliminary action during manufacturing to create wiring layers with optimal geometry (small taper angles and uniform thickness). This preliminary structural optimization reduces stress and electric field concentration that would otherwise cause threshold voltage shifts during long-term operation, thereby maintaining reliability

Inventive Principle:
Principle #10Preliminary action

4Ease of manufacture

If the taper angle of wiring layers is large, then the manufacturing process is simpler, but the coverage of subsequent layers is poor

Engineering Contradiction:
Improvewiring layer formation simplicityVSAvoidlayer coverage
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The manufacturing process is segmented into two etching steps. The first step forms the wiring layers with controlled small taper angles, and the second step refines the structure. This segmentation enables better coverage for subsequent layers while maintaining manufacturing feasibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first etching step performs a partial etching action that creates the basic wiring layer structure with appropriate taper angles. The second etching step then performs an additional refinement action, ensuring adequate coverage without requiring the first step to achieve perfect geometry alone

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in transistors with high reliability and stable switching characteristics, as evidenced by minimal shifts in threshold voltage during bias-thermal stress tests, and reduces unevenness in the semiconductor layer thickness, improving overall transistor performance.

Implementation Method 1

a first etching, in which an etching rate for a film to be etched is higher than an etching rate for a layer formed beneath the film to be etched

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

a second etching, in which etching rates for the film to be etched and the layer formed beneath the film to be etched are higher than those of the first etching

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS8597992B2Transistor and manufacturing method of the same
Publication Date: 2013.12.03 SEMICON ENERGY LAB CO LTD
  • US8597992B2 patent drawing
  • US8597992B2 patent drawing
  • US8597992B2 patent drawing

AI summary

A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.