Transistors with Floating Nodes for ESD Protection
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Solution Overview
Problem
Semiconductor devices face significant challenges in providing effective electrostatic discharge protection, especially for high-voltage applications, as existing solutions either increase chip size or fail to prevent current leakage during electrostatic discharge events.
Innovation Solution
The semiconductor device incorporates a plurality of transistors with a common gate, first and second source/drain (S/D) contacts, and floating nodes, where the second S/D contacts are disposed over carrier-doped regions within the substrate, and the floating nodes facilitate defining these regions, thereby reducing current leakage and enhancing electrostatic discharge protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrostatic discharge protection structures are added to semiconductor devices, then electrostatic discharge protection capability is improved, but chip size increases
Solution Approach 1:
The invention divides the electrostatic discharge protection function into multiple discrete carrier-doped regions distributed among the transistors, rather than using a single large protection structure. Each transistor or group of transistors has its own dedicated carrier-doped regions, which segment the overall protection mechanism into smaller, more space-efficient units that collectively provide comprehensive ESD protection across the chip.
Solution Approach 2:
The invention implements electrostatic discharge protection locally at each transistor level by adding carrier-doped regions specifically to transistors that require protection. This allows ESD protection to be applied only where needed rather than uniformly across the entire chip, optimizing the balance between protection capability and chip area utilization.
2Reliability
If conventional electrostatic discharge protection structures are added to semiconductor devices, then electrostatic discharge protection capability is improved, but fabrication cost increases
Solution Approach 1:
The invention merges the electrostatic discharge protection function with the existing transistor structure by integrating carrier-doped regions directly into the transistor fabrication process. The carrier-doped regions are formed using the same doping processes and mask layers already required for transistor creation, thereby combining ESD protection fabrication with standard transistor manufacturing without requiring separate dedicated fabrication steps.
Solution Approach 2:
The invention makes the transistor structure itself multi-functional by enabling it to serve both its primary switching function and an electrostatic discharge protection function simultaneously. The carrier-doped regions enable transistors to provide ESD protection in addition to their normal operation, eliminating the need for separate dedicated ESD protection structures and reducing overall fabrication complexity.
3Reliability
If existing electrostatic discharge protection methods are used, then some protection is provided, but current leakage occurs during electrostatic discharge events
Solution Approach 1:
The invention changes the electrical parameters of the transistor by adding carrier-doped regions, which modify the carrier concentration and electrical characteristics in specific areas. This parameter modification creates potential barriers that effectively control current flow during electrostatic discharge events, preventing harmful current leakage while maintaining normal transistor operation under standard conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively limits current flow during electrostatic discharge events, preventing damage to transistors and allowing the device to sustain higher voltage stresses without increasing chip size, thus providing improved electrostatic discharge protection for high-voltage applications.
Implementation Method 1
Damage to semiconductor devices from electrostatic discharge (ESD) can occur at any point, from manufacture to field service. An electrostatic discharge is defined as a transfer of charge between bodies at different electrical potentials.
Implementation Method 2
the plurality of second S/D contacts being disposed over a plurality of carrier-doped regions within the substrate
Data Source
AI summary
High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.