Transition Encoding Codes for Reliable Clock Recovery
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Solution Overview
Problem
In electronic data communications, clock recovery processes can fail due to excessively long run lengths of data sequences without sufficient transitions, leading to synchronization issues between senders and receivers.
Innovation Solution
The implementation of a system that encodes digital data to ensure a limited run length by using a processing circuit to identify and encode original data into encoded payload words, eliminating all-zero and all-one words, thereby guaranteeing transitions every K bits, using a one-to-one mapping with absent values as encoder values and transmitting these values along with the encoded data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted without encoding to preserve original data integrity, then data accuracy is maintained, but run length may exceed limits causing clock recovery failure
Solution Approach 1:
The patent applies parameter changes by modifying the data representation parameters through encoding schemes that transform original data into encoded forms with controlled run lengths. The encoder changes the parameter space by mapping original q-bit values to encoded q-bit values using absent values D1 and D2, ensuring the encoded data maintains reliability for clock recovery while minimizing information loss through efficient encoding.
2Reliability
If encoding is applied to limit run length, then clock recovery reliability is improved, but device complexity increases due to encoding/decoding operations
Solution Approach 1:
The patent applies segmentation by dividing the encoding process into distinct functional blocks: an encoder that performs the one-to-one mapping using absent values, a packet assembly unit that organizes encoded words into packets with keys, and a decoder that reverses the process. This segmentation allows each component to be optimized independently, managing device complexity while achieving reliable synchronization through systematic run length control.
Data Source
AI summary
A processing circuit configured to: receive original data; partition the original data into a plurality of original q-bit words; assemble a data packet including N original q-bit words from the plurality of original q-bit words; identify a first encoder value and a second encoder value that are absent from the values of the N original q-bit words; encode the N original q-bit words based on a one-to-one mapping from q-bit original values to q-bit encoded values based on the first encoder value and the second encoder value to generate N encoded q-bit payload words, the N encoded q-bit payload words being free of words that are all-zeroes and free of words that are all-ones; generate a key representing the first encoder value and the second encoder value; and transmit the key and the N encoded q-bit payload words.