Transition Fault Testing of Asynchronous IC Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current at-speed test techniques for integrated circuits fail to effectively handle functionally asynchronous paths, leading to reduced test quality, increased pattern count, and yield loss due to the inability to test these paths at their designated clock speeds, resulting in false positives and negatives.
Innovation Solution
A test circuit with a configuration register that specifies differing clock sources for dynamic and static circuit paths, allowing for functional testing of all paths at their respective designated speeds, thereby eliminating the need for pattern masking and clock gating, and enhancing test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single clock source is used for all logic paths during testing, then the testing system is simple to operate, but functionally asynchronous paths cannot be tested at their designated clock speeds leading to reduced test quality
Solution Approach 1:
The testing system dynamically selects different clock sources based on the type of path being tested. The configuration register allows the system to switch between a first clock source for dynamic paths and a second clock source for functionally asynchronous paths, making the clock selection adaptive rather than fixed.
Solution Approach 2:
Different clock sources are assigned to different paths based on their specific requirements. Dynamic paths receive one clock source while functionally asynchronous paths receive another, allowing each path to be tested with the appropriate clock characteristics for its functional behavior.
2Device complexity
If functionally asynchronous paths are not handled correctly during scan-based at-speed test pattern generation, then the testing process is simple, but test quality decreases due to false positives and negatives
Solution Approach 1:
The configuration register is pre-configured with the clock source assignments for different path types before testing begins. This preliminary setup ensures that the correct clock sources are automatically applied during test pattern generation, preventing false results without requiring complex real-time analysis.
3Reliability
If pattern masking and clock gating are used to handle functionally asynchronous paths, then false positives are reduced, but the pattern count increases and ATPG coverage degrades
Solution Approach 1:
The invention changes the clock source parameter for functionally asynchronous paths rather than using pattern masking. By providing a dedicated second clock source configured in the configuration register, the system can properly test these paths without requiring additional care bits or masking operations, thus maintaining ATPG coverage.
Data Source
AI summary
A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.