Semiconductor Transition Layer Thickness via Conductive Roughness

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Solution Overview

Problem

In semiconductor manufacturing, the transition layer in both the array region and peripheral circuit region of DRAMs has the same thickness, leading to suboptimal conductivity in the array region and potential current leakage in the peripheral circuit region due to excessive thickness.

Innovation Solution

A method is developed to form transition layers of different thicknesses in the array and peripheral circuit regions by treating the first conductive layer with ion implantation to increase its roughness, followed by forming a transition layer that reacts with the semiconductor substrate, ensuring the transition layer is thicker in the array region for improved conductivity and thinner in the peripheral circuit region to prevent current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a uniform thickness transition layer is formed in both array and peripheral circuit regions, then the manufacturing process is simple, but the conductivity in the array region is insufficient and current leakage occurs in the peripheral circuit region

Engineering Contradiction:
Improveconductivity in array regionVSAvoidtransition layer thickness control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by creating different transition layer thicknesses in different regions: the array region receives a thicker transition layer (50-150nm) to improve conductivity, while the peripheral circuit region receives a thinner transition layer (10-50nm) to prevent current leakage. This is achieved through selective ion implantation that modifies the first conductive layer's roughness only in the array region, causing the transition layer to deposit differently in each region during the same deposition process.

Inventive Principle:
Principle #3Local quality

2Reliability

If the transition layer thickness is increased to improve conductivity, then electrical performance improves, but current leakage increases in the peripheral circuit region

Engineering Contradiction:
Improveelectrical conductivityVSAvoidcurrent leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent resolves this contradiction by making the transition layer thickness location-dependent: thicker (50-150nm) in the array region where high conductivity is needed, and thinner (10-50nm) in the peripheral circuit region where current leakage must be prevented. The selective ion implantation creates regional differences in the first conductive layer, which then guide differential transition layer formation.

Inventive Principle:
Principle #3Local quality

3Reliability

If different thicknesses of transition layer are formed in array and peripheral circuit regions, then conductivity and current leakage control are optimized, but the manufacturing process becomes more complex

Engineering Contradiction:
Improveelectrical performanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges multiple functions into a single ion implantation step: it simultaneously modifies the first conductive layer's properties in the array region to enable subsequent differential transition layer formation, and prepares the peripheral circuit region to receive a thinner transition layer. This consolidation achieves regional thickness differentiation without adding separate deposition or etching steps for each region.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The ion implantation step is performed as a preliminary action before transition layer deposition. This preliminary treatment selectively modifies the first conductive layer in the array region, creating the conditions necessary for the transition layer to form with different thicknesses in different regions during the subsequent deposition process.

Inventive Principle:
Principle #10Preliminary action

4Manufacturing precision

If ion implantation is performed to increase roughness of the first conductive layer, then transition layer thickness differentiation is achieved, but additional process steps are required

Engineering Contradiction:
Improvetransition layer thickness controlVSAvoidnumber of process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the ion implantation step with the existing manufacturing flow, merging the roughness modification function into a single additional process step that serves multiple purposes: it prepares the array region for thicker transition layer formation, differentiates it from the peripheral circuit region, and enables subsequent selective deposition without requiring separate processing sequences.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the conductivity in the array region while avoiding current leakage in the peripheral circuit region, thereby improving the overall performance of the semiconductor structure without adding complex processes.

Implementation Method 1

the step of treating the first conductive layer further includes that: ion implantation is performed to the first conductive layer to damage surface evenness of the first conductive layer and increase the roughness of the first conductive layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

cobalt reacts with the first conductive layer and the semiconductor substrate to form the transition layer

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS12108594B2Semiconductor device manufacturing method comprising first conductive layer with increased roughness in array region
Publication Date: 2024.10.01 CHANGXIN MEMORY TECH INC
  • US12108594B2 patent drawing
  • US12108594B2 patent drawing
  • US12108594B2 patent drawing

AI summary

A semiconductor manufacturing method includes: providing a semiconductor substrate, in which the semiconductor substrate includes an array region and a peripheral circuit region, in the array region, multiple capacitor contact holes are on the semiconductor substrate, and a first conductive layer is deposited on a bottom of each of the capacitor contact hole, and in the peripheral circuit region, a device layer is on the semiconductor substrate; treating the first conductive layer to increase its roughness; forming wire contact holes exposing the semiconductor substrate in the peripheral circuit region; forming a transition layer that at least covers a surface of the first conductive layer and a surface of the semiconductor substrate exposed by the wire contact holes; and forming a second conductive layer that covers the transition layer, and fills the capacitor contact holes and the wire contact holes.