Transition-Triggered Synchronizer Clocking for Low-Power CDC
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Solution Overview
Problem
Metastability issues arise during data transfer between subsystems of a system on a chip (SoC) when they operate on different clock signals, leading to parasitic power dissipation, particularly in battery-powered devices.
Innovation Solution
A gated clock is generated to drive a bank of synchronizers coupled between input and output data lines, enabling the synchronizers only for a short period after detecting signal transitions and disabling them until the next transition is detected, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronizers are continuously enabled to prevent metastability during data transfer between different clock domains, then data transfer reliability is improved, but power consumption increases
Solution Approach 1:
The synchronizer is enabled periodically only when data transitions are detected between clock domains, rather than running continuously. The clock gate circuitry generates enable signals based on transition detection, causing the synchronizer to operate in periodic bursts only when necessary for data transfer, thus reducing overall power consumption while maintaining reliability during actual data transfers
Solution Approach 2:
The system uses its own data transition signals to automatically control the enabling of the synchronizer. The transition detection circuitry monitors the data bus and self-generates the enable signal for the clock gate, eliminating the need for external control signals and allowing the system to autonomously manage power consumption based on actual data transfer needs
2Loss of energy
If synchronizers are disabled to reduce power consumption during idle periods, then power efficiency is improved, but metastability risks increase during active data transfer
Solution Approach 1:
The system implements feedback through transition detection circuitry that continuously monitors data bus activity and feeds this information back to the clock gate enable logic. When transitions are detected indicating active data transfer, the feedback signal automatically enables the synchronizer to prevent metastability. When no transitions occur, the synchronizer remains disabled to save power, thus dynamically balancing power efficiency and reliability based on real-time system state
Solution Approach 2:
The transition detection circuitry operates continuously to detect data changes before they reach the synchronizer. By detecting transitions in advance and proactively enabling the synchronizer before potential metastability issues can occur, the system ensures reliability is maintained during data transfer while allowing power savings during idle periods when no transitions are detected
Data Source
AI summary
A device includes input data lines associated with a first time domain and output data lines associated with a second time domain. Synchronizing circuitry is coupled between the input data lines and output data lines. The synchronizing circuitry is driven by a synchronizing clock signal generated by clock generating circuitry. The clock generating circuitry is coupled to the input data lines and the synchronizing circuitry. In operation, the clock generating circuitry detects signal transitions on the plurality of input data lines. The clock generating circuitry generates the synchronizing clock signal that drives the synchronizing circuitry based on detected transitions, a clock signal of the first time domain, and a clock signal of the second time domain.