Translation Agent Hardware Isochronous Caching Priority
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Solution Overview
Problem
Accessing system memory is time-consuming and resource-intensive due to redundant translation information retrieval, which slows down real-time response in isochronous devices like video and audio players and USB devices.
Innovation Solution
A translation agent hardware with a cache memory that prioritizes isochronous caching, using LRU index values to manage cache lines and a counter to reserve cache lines for isochronous devices, reducing redundant system memory access by caching translation information and physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translation information is stored in system memory and accessed during address translation, then the translation information is available for use, but the access time increases and response speed decreases
Solution Approach 1:
The patent pre-loads translation information from system memory into the cache memory before it is actually needed for address translation. This preliminary action ensures that when address translation is required, the translation information is already available in the cache, eliminating access delays and improving response speed for isochronous devices.
Solution Approach 2:
The patent introduces a cache memory as an intermediary component between the system memory and the address translation process. This cache memory stores translation information locally, acting as a buffer that mediates between the slow system memory and the fast address translation requirement, thereby reducing access time while maintaining information availability.
2Speed
If cache memory is used to store translation information, then access speed improves, but device complexity increases
Solution Approach 1:
The patent segments the memory system into two distinct parts: system memory for storing all translation information and cache memory for storing frequently used translation information. This segmentation allows the system to benefit from fast cache access while maintaining the capacity of system memory, achieving improved access speed without requiring a complete redesign of the memory architecture.
Solution Approach 2:
The patent applies local quality by making the cache memory a localized, small-capacity storage unit within the translation agent that provides fast access to specific translation information. Instead of making the entire system memory fast, only the frequently accessed translation information is stored locally in the cache, optimizing speed where it matters most while keeping overall device complexity manageable.
3Adaptability or versatility
If cache lines are allocated to non-isochronous devices, then those devices can access translation information, but isochronous devices may experience delays when cache lines are released
Solution Approach 1:
The patent implements dynamic cache line management where the LRU index values are adjusted based on device type. When an isochronous device needs translation information, the system dynamically identifies and releases cache lines with higher LRU indices that belong to non-isochronous devices, ensuring real-time response for isochronous devices while maintaining flexible cache allocation overall.
Solution Approach 2:
The patent uses feedback mechanisms through LRU (Least Recently Used) indexing to monitor cache line usage patterns. When isochronous devices require translation information, the system checks LRU indices and selectively releases cache lines from non-isochronous devices, using the LRU feedback information to make intelligent cache management decisions that prioritize real-time response requirements.
Data Source
AI summary
An acceleration technology for accessing system memory, which provides translation agent hardware that calculates the physical address of the system memory based on an access request issued from the device end. The translation agent hardware has a cache memory that stores information to speed up the calculation of the physical address. Each cache line corresponds to a last-recently used (LRU) index value, and the cache line with the greatest LRU index value is preferentially released to be reassigned. A counter counts a count value to show an isochronous caching demand. LRU index values of cache lines assigned to non-isochronous caching are kept not lower than the count value, and thereby isochronous caching takes precedence over non-isochronous caching.