Address Translation Cache Invalidation for Partial Page Table Changes
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Solution Overview
Problem
Existing data processing systems face challenges in efficiently managing address translations due to the difficulty in allocating contiguous memory for large address translation data and the unnecessary invalidation of full address translation data when only partial data changes.
Innovation Solution
Implementing a partial-address-translation-invalidation (PATI) request that selectively invalidates partial address translation data in the address translation cache without affecting full data, using cache control circuitry to identify and invalidate only the necessary cache entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional address translation cache invalidation is performed when page table entries change, then address translation consistency is maintained, but full address translation data is unnecessarily invalidated even when only partial data changes
Solution Approach 1:
The patent segments address translation data into two distinct types: partial address translation data (pointing to next-level page tables) and full address translation data (providing complete output addresses). The invalidation mechanism is also segmented to selectively invalidate only the affected type based on the nature of the page table entry change, rather than invalidating all cache entries uniformly.
Solution Approach 2:
The patent implements partial invalidation action by invalidating only the necessary portion of cache entries (those containing partial address translation data) when page table entries change, rather than performing excessive full invalidation of all address translation cache entries. This reduces unnecessary cache misses and improves performance.
2Quantity of substance
If contiguous memory is allocated for large address translation data, then address translation coverage is sufficient, but memory allocation difficulty and fragmentation increase
Solution Approach 1:
The patent divides the address translation data structure into a multi-level hierarchy, where each level contains a manageable subset of translation entries. This segmentation allows the system to achieve comprehensive address translation coverage without requiring a single large contiguous memory block, as each level can be allocated independently in smaller memory segments.
Solution Approach 2:
The patent transitions from a single-dimensional flat address translation structure to a multi-dimensional hierarchical structure. This dimensional change allows the system to organize address translation data across multiple levels and memory regions, achieving full coverage while avoiding the need for large contiguous memory allocations at any single level.
3Speed
If address translation cache stores all address translation data, then translation speed is improved, but cache size and memory usage increase
Solution Approach 1:
The patent segments the address translation cache into multiple levels, with each level storing a subset of address translation data. This segmentation allows the system to maintain fast translation by keeping frequently accessed translations in smaller, faster cache levels, while less frequently accessed data resides in larger, slower memory levels, optimizing the trade-off between speed and memory usage.
Solution Approach 2:
The patent implements a nested cache structure where smaller address translation caches are embedded within larger memory structures. This nested arrangement allows the system to provide fast translation for common cases using the inner smaller caches, while falling back to outer larger memory structures for less common translations, achieving fast performance without requiring the entire address space to be cached at the fastest level.
Data Source
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AI summary
Partial-address-translation-invalidation request to cause cache control circuitry to: identify whether a given cache entry of the address translation cache is a target cache entry to be invalidated, wherein the target cache entry comprises a cache entry for which the address translation data comprises partial address translation data indicative of an address of the next level page table specified by a table address of a target page table entry when used as the branch page table entry; and trigger an invalidation of the given cache entry when the given cache entry is identified to be the target cache entry. The given cache entry is permitted to be retained when the given cache entry provides full address translation data indicative of an address of a corresponding region of address space corresponding to an output address specified by the target page table entry when used as the leaf page table entry.