Address Translation Cache With PRI Handling for DMA Page Misses
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Solution Overview
Problem
The continuous need for translation agent (TA) involvement in address translation requests creates bottlenecks in memory sub-system performance, affecting speed, latency, and quality-of-service, especially in systems with large submission and completion queues and increased media speeds.
Innovation Solution
Implementing an address translation cache (ATC) within the controller to store address translations for future access, and incorporating a page request interface (PRI) handler to automate page miss requests, reducing the need for host memory pinning and optimizing DMA operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If translation agent (TA) involvement is maintained for all address translation requests, then address translation accuracy is ensured, but memory sub-system performance deteriorates due to bottlenecks in speed, latency, and quality-of-service
Solution Approach 1:
An address translation cache (ATC) is introduced as an intermediary component between the host interface circuits and the translation agent. The ATC stores previously translated virtual addresses and their corresponding physical addresses, allowing the system to retrieve translations locally without always involving the TA. This mediator approach maintains translation accuracy by validating cache entries through the TA when needed while significantly improving performance by avoiding repeated TA involvement for cached addresses.
Solution Approach 2:
The system performs preliminary address translation by proactively storing virtual-to-physical address mappings in the ATC before they are needed for subsequent operations. When address translation requests are received, the system first checks the ATC for pre-computed translations, executing the translation action in advance and storing it for future rapid access, thereby reducing latency and improving throughput.
2Reliability
If host memory pinning is used to ensure page availability, then DMA operation reliability is improved, but host memory resources are consumed increasing system complexity
Solution Approach 1:
The address translation cache implements a self-service mechanism where the controller automatically manages address translation lookups and page availability checks without requiring host memory pinning. The ATC independently tracks virtual-to-physical address mappings and handles translation requests, freeing the host memory management system from the complexity of pinning operations while ensuring DMA reliability through cached translation information.
Data Source
AI summary
A system includes a controller memory, coupled to host interface circuits, to store a host request queue to buffer a page request group of page miss requests associated with page miss messages received from a host interface circuit and an outbound queue to buffer memory commands directed to a host system. An outbound buffer buffers page request groups received from the host request queue and the memory commands received from the outbound queue. An outbound queue handling logic determines the outbound buffer contains a first page request group and causes the page miss requests of the first page request group to be sent to a translation agent of the host system, causing the translation agent to re-pin a physical page of memory to each respective virtual address of respective page miss requests.