Translation Cache With Striped ECC Layout for Lower Memory Overhead
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Solution Overview
Problem
Modern memory subsystems face challenges in reducing ECC memory overhead, particularly with the increasing demand for full SDDC capability as future generations of memory devices may not have enough ECC bits available, and existing solutions require significant changes to processor cores.
Innovation Solution
Implementing a translation cache and configurable ECC memory system that uses a striped ECC storage scheme, allowing ECC trees for two segments of a cache line to be stored in the same ECC DRAM, reducing the number of DRAMs needed without altering the processor core architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC memory allocation is used with fixed-size cache lines, then full SDDC capability is achieved, but ECC memory overhead increases by 25%
Solution Approach 1:
The cache line is divided into multiple segments (e.g., two 32-byte segments from a 64-byte cache line), and ECC trees for these segments are stored in the same ECC memory location using a striped storage scheme. This segmentation allows efficient utilization of ECC memory resources while maintaining full SDDC capability for each segment.
Solution Approach 2:
ECC trees for multiple cache line segments are merged into the same ECC memory location rather than allocating separate ECC memory for each segment. The striped ECC storage scheme combines storage of multiple segments' ECC data in a unified memory structure, reducing overall ECC memory overhead while preserving error correction capability.
2Reliability
If more ECC bits are allocated to future memory devices, then full SDDC capability is maintained, but available bits for other applications (poisoning, directories, security) decrease
Solution Approach 1:
The invention changes the organizational parameters of ECC memory storage by implementing a striped storage scheme that maps multiple cache line segments to shared ECC memory locations. This parameter change allows the same ECC bits to serve multiple segments simultaneously, effectively increasing the available ECC coverage without requiring additional physical ECC bits, thereby freeing up bits for other applications.
3Quantity of substance
If processor core architecture is altered to reduce ECC overhead, then ECC memory efficiency improves, but device complexity increases
Solution Approach 1:
The invention introduces an intermediary layer (the striped ECC storage scheme and associated mapping logic) between the processor core and the physical ECC memory allocation. This intermediary handles the complexity of managing shared ECC resources for multiple segments, allowing the processor core to maintain its simple fixed-size cache line architecture while still achieving reduced ECC overhead through the intermediary's intelligent resource management.
Data Source
AI summary
A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).