Translation Circuitry Error Detection Code Integrity
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Solution Overview
Problem
Existing data processing systems face challenges in ensuring error-free translation of data, particularly in safety-critical contexts where redundancy-based techniques are costly and less attractive due to area and power overheads, and existing error detection methods are vulnerable to variations during storage and transmission.
Innovation Solution
The system generates an error detection code based on both input and translated data, allowing for verification and signaling of errors, and includes additional attribute information for enhanced protection, using translation circuitry to perform translations and store configuration data with associated error detection codes for integrity checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy-based techniques (e.g., dual-core-lock-step) are used to achieve high fault detection rates, then reliability is improved, but area and power overhead increase
Solution Approach 1:
The patent uses error detection codes as virtual copies of the translation configuration data to verify integrity. Instead of physically duplicating the translation logic (spatial redundancy), the system creates computational copies (error detection codes) that can validate the original data without requiring additional hardware resources for redundancy
Solution Approach 2:
The patent replaces the mechanical/hardware-based redundancy system with an information-theoretic approach using error detection codes. Instead of duplicating physical translation circuits, the system uses mathematical transformations (error detection code generation and verification) to achieve the same reliability goal with minimal hardware overhead
2Reliability
If redundancy-based techniques are used to achieve high fault detection rates, then reliability is improved, but power consumption increases
Solution Approach 1:
The system uses error detection codes as lightweight virtual copies for verification purposes. These codes require minimal computational resources to generate and verify compared to running duplicate translation circuits, thereby significantly reducing power consumption while maintaining reliability
Solution Approach 2:
The patent substitutes energy-intensive hardware redundancy with low-power information processing. The error detection code mechanism requires only simple mathematical operations rather than full translation circuit operations, dramatically reducing the power overhead while achieving comparable or superior fault detection capability
3Reliability
If error detection code is stored with translation configuration data, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent merges the error detection code with the translation configuration data into a single stored entity. This combination allows the verification mechanism to be integrated with the existing data storage structure, adding integrity checking capability without requiring completely separate storage subsystems or complex management overhead
Solution Approach 2:
The stored data structure serves multiple functions: it contains both the translation configuration information needed for address translation and the error detection code needed for integrity verification. This multi-functionality reduces the need for separate dedicated verification storage, thereby minimizing the increase in device complexity
Data Source
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Figure 3A~3B
AI summary
An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data. A difference between the associated error detection code and the verification error detection code triggers an error in the translation response.