Translation Layer for 3D IC Test Pattern Composition
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Solution Overview
Problem
Current 3D integrated circuit (IC) design and testing methods face challenges in managing complexity, time-to-market pressure, and test cost due to limitations in existing design-for-test (DFT) and automatic test pattern generation (ATPG) techniques, which struggle with communication constraints and inefficient test data utilization.
Innovation Solution
A compositional ATPG approach that uses a translation layer to resolve communication constraints between cores, allowing for the composition of test patterns without design netlists, and a modular test platform with a token-based distributed system for efficient test data delivery and high test pattern utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If conventional ATPG methods are used for 3D IC testing, then test pattern generation can be automated, but test development time and effort increase with system size and complexity
Solution Approach 1:
The patent segments the 3D IC system into multiple cores and applies ATPG independently to each core rather than treating the entire system as one unit. This segmentation allows parallel test pattern generation for each core, significantly reducing overall test development time while maintaining automation. The test patterns for individual cores are then composed to form system-level test patterns.
Solution Approach 2:
The patent performs preliminary action by generating test patterns for each core independently before composing them into system-level test patterns. This preliminary core-level ATPG allows the system to benefit from automation at the core level while avoiding the computational complexity of generating test patterns for the entire 3D IC system at once, thus reducing test development time.
2Extent of automation
If conventional ATPG methods are used for 3D IC testing, then test pattern generation can be automated, but test development effort increases with system size and complexity
Solution Approach 1:
The patent segments the complex 3D IC testing task into manageable core-level ATPG operations. By dividing the system into independent cores, the complexity of test development is reduced from system-level to core-level, making automation more feasible and reducing the overall development effort required for large-scale 3D IC systems.
Solution Approach 2:
The patent introduces an intermediary composition step that combines independently generated core-level test patterns into system-level test patterns. This intermediary process simplifies the overall test development effort by avoiding direct system-level ATPG complexity while maintaining automation through standardized composition operations.
3Ease of manufacture
If test isolation methods are used to partition the system, then ATPG can be applied to subsystems, but cores are unnecessarily isolated from their system environment
Solution Approach 1:
The patent segments the system into cores for independent ATPG application while maintaining adaptability through a composition framework. This segmentation enables ease of manufacture by allowing standard ATPG tools to be applied to each core, while the composition step restores flexibility by enabling system-level test pattern generation that accounts for inter-core interactions.
Solution Approach 2:
The patent performs preliminary ATPG on isolated cores and then applies a composition operation to integrate them into system-level test patterns. This preliminary isolation facilitates automated test generation, while the subsequent composition action restores flexibility by incorporating system environment considerations, thus resolving the contradiction between ease of manufacture and adaptability.
4Reliability
If conventional DFT methods are used, then testing can be performed, but test data utilization is inefficient and test cost increases
Solution Approach 1:
The patent merges independently generated core-level test patterns into unified system-level test patterns through composition. This merging increases test data utilization efficiency by ensuring that test data delivered to the system is optimally used across multiple cores, reducing redundancy and lowering test cost while maintaining comprehensive testing capability.
Solution Approach 2:
The patent creates universal test patterns at the core level that can be reused and composed for different system configurations. This multi-functionality increases test data utilization efficiency by allowing the same core-level test patterns to serve multiple purposes in different system contexts, thereby reducing test cost while maintaining reliable testing.
Data Source
AI summary
The translation based test architecture translates inputs, test control signals, and the chip pin IOs. Translation of test control signals derives dedicated local test control signals for each individual circuit-under-test (CUT) can introduce programmability directly into the test pattern transformation and composition. Using the local test control signals realizes a diversified test functions in each individual CUT without increasing test resource requirement. The translation of IO enable signals of chips can be used to create test scenarios in multi-chip module systems. Transformation of the generated test patterns to derive new test patterns occurs by retranslation of the signals within the generated test patterns. The retranslation can be reassigning test data of the translation layer cells in the generated test patterns and adjustment of corresponding difference in the test patterns. To achieve retranslation, the translation layer cells are identified in the test patterns.