Translation Layer for 3D IC Test Pattern Composition
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Solution Overview
Problem
Current 3D IC design and testing methods face challenges in managing complexity and time-to-market pressures, leading to high test development costs and inefficiencies due to the need for complex test pattern generation and the isolation of cores from their system environment, which limits test data utilization and at-speed test coverage.
Innovation Solution
A compositional approach to automatic test pattern generation (ATPG) that uses a translation layer to resolve communication constraints between cores, allowing for the composition of test patterns without design netlists, enabling continuous execution of core tests and maximizing test data utilization through a modular test platform with a token-based distributed system for flexible test data delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional test isolation methods are used to partition the system into subsystems for ATPG, then test development complexity is reduced, but test data utilization is limited and at-speed test coverage of interface logic is lost
Solution Approach 1:
The patent introduces a translation layer as an intermediary component between cores that enables test pattern composition without isolation. This translation layer resolves communication constraints between cores by translating test patterns, allowing cores to be tested in their system environment while maintaining manageable complexity through modular translation logic.
Solution Approach 2:
The patent segments the test development process into two independent phases: core-level ATPG (which remains simple and isolated) and system-level test pattern composition (which handles integration). This segmentation allows each phase to be optimized independently, reducing overall complexity while maintaining high test data utilization through the composition phase.
2Reliability
If generation-based ATPG is used for the entire 3D IC design, then comprehensive test coverage is achieved, but test development time and computational effort increase significantly
Solution Approach 1:
The patent performs preliminary ATPG at the core level to generate test patterns for individual cores before system integration. These pre-generated core test patterns are then composed and translated for system-level testing, avoiding the need to perform expensive full-system ATPG from scratch while maintaining comprehensive coverage through the composition process.
Solution Approach 2:
The patent merges independently generated core test patterns into system-level test patterns through a composition process. This combining approach reuses the computational work already done at the core level, significantly reducing overall test development time while achieving comprehensive system coverage by integrating multiple core test patterns.
3Device complexity
If cores are isolated from their system environment for testing, then ATPG complexity is reduced, but flexibility in achieving high test data utilization is limited
Solution Approach 1:
The patent introduces dynamic test pattern translation that adapts to different system configurations and communication constraints. The translation layer can dynamically adjust test patterns based on the specific inter-core communication requirements, providing flexibility while maintaining manageable ATPG complexity through the modular translation approach.
Solution Approach 2:
The patent changes the parameters of test patterns through the translation layer, transforming core-level test patterns into system-level test patterns that satisfy communication constraints. This parameter transformation enables flexibility in achieving high test data utilization without requiring complex re-generation of test patterns, as the translation process adapts existing patterns to system requirements.
Data Source
AI summary
The Translation Layer is embedded into each circuit under test (CUT) to modularize test process. The modularized tests are self-contained and performed in isolation. They are composed without consideration of environment constraints. The CUT and its environment constraints can be concurrently be tested in isolation and independently. Interconnections between the CUT and the environment can be tested in the environment constraint test without additional dedicated test logic. The modularized test process allows the test patterns of the environment constraints to be derived from those of the CUT. The resulting test patterns are used to compose the test patterns of a target system. Since the test process is recursive in nature, the modularized test of each constituent subsystem or design core can be performed in isolation in the target system, while the environment constraints and the interconnections are being tested concurrently.