Translinear Cell Biasing for Analog Multiplier Accuracy
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Solution Overview
Problem
Analog multiplier/divider circuits face inaccuracies due to non-ideal effects like the Early and Beta effects, especially when the dynamic range of current sources is large, leading to unbalanced collector-to-emitter voltages and errors in output current.
Innovation Solution
A translinear cell formed by four bipolar junction transistors with dynamic biasing using NMOSFETs and PMOSFETs to maintain equal collector-to-emitter voltages across BJTs, along with a current clamping circuit to restrict output current to a maximum value, balances the Early effects and enhances accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the dynamic range of current sources is increased, then the versatility and adaptability of the analog multiplier/divider is improved, but inaccuracies due to unbalanced collector-to-emitter voltages and Early effects worsen
Solution Approach 1:
The patent dynamically adjusts the biasing conditions of the BJT transistors by changing the collector-to-emitter voltages to maintain equality across all transistors in the translinear cell. This is achieved through additional biasing circuitry that monitors and equalizes the voltage drops, allowing the circuit to maintain accuracy across a wide dynamic range of current sources.
Solution Approach 2:
The patent employs feedback mechanisms where the collector-to-emitter voltages of the BJT transistors are continuously monitored and used to adjust the biasing conditions. This feedback loop ensures that even when current sources operate over a wide dynamic range, the voltages remain balanced, preventing Early effects from degrading the output current accuracy.
2Device complexity
If the Early effects are not balanced, then the circuit operation is simpler, but errors in output current increase
Solution Approach 1:
The patent introduces dynamic biasing that adjusts the collector-to-emitter voltages of the BJT transistors to maintain equality. This parameter adjustment equalizes the Early effects across all transistors, reducing output current errors while managing the additional circuit complexity through systematic voltage equalization.
Solution Approach 2:
The patent creates equipotential conditions by ensuring that all BJT transistors in the translinear cell operate at equal collector-to-emitter voltages. This equipotential approach balances the Early effects and reduces output errors, as the additional biasing circuitry actively maintains equal voltage levels across all transistor collectors.
3Measurement precision
If current clamping is implemented, then output current accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent implements current clamping by dynamically adjusting the biasing parameters to restrict the output current to a predetermined maximum value. This parameter control improves accuracy by preventing saturation effects and ensuring linear operation, while the complexity is managed through integrated biasing circuitry that works seamlessly with the translinear cell.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dynamic biasing and current clamping circuitry ensure accurate output current by balancing the Early effects across BJTs, maintaining precision even with wide dynamic ranges of current sources, thereby improving the accuracy of the analog multiplier/divider circuits.
Implementation Method 1
A circuit comprising a translinear cell implements an analog multiplier/divider that provides an output signal, for example a current that is the product of the current in a first current source multiplied by the current in a third current source divided by the current in a second current source. The translinear cell is formed by suitably connecting four bi-polar junction transistors (BJTs).
Implementation Method 2
Non-ideal effects associated with the BJT transistors, for example the Early and BETA effects, introduce inaccuracies in the function of the circuit. In examples, the non-ideal effects are more evident when the dynamic range of the current in the current sources is large, possibly resulting in unacceptable inaccuracies.
Data Source
AI summary
A power factor correction (PFC) integrated circuit having a feed forward circuit. The feed forward circuit comprises a first current source, a second current source, and a third current source, a first bi-polar junction transistor (BJT), a second BJT, a third BJT, and a fourth BJT coupled together in a translinear cell, where the first current source is coupled to the first BJT, the second current source is coupled to the second BJT, and the third current source is coupled to the third BJT, a biasing network coupled to the first BJT and to the second BJT and configured to maintain equal collector-to-emitter voltage across the first BJT and the second BJT, where the feed forward circuit is configured to output a current based on a current of the first current source, a current of the third current source, and a current of the second current source.