Transmission Circuit Phase Adjustment for High-Speed Data Reception
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Solution Overview
Problem
High-frequency clock signals cause an increased occurrence rate of reception errors when phase-shifted, particularly at high frequencies, leading to inefficiencies in data transmission.
Innovation Solution
A transmission circuit that generates a first clock signal and a second clock signal with a lower frequency, using conversion circuits to narrow bit width and capture data sequences for analysis, with a phase adjusting circuit to optimize the phase of the second clock signal based on analysis results, thereby reducing bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-frequency clock signal is used for data transmission, then transmission speed is improved, but the occurrence rate of reception errors increases due to phase shifts
Solution Approach 1:
The patent implements dynamic phase adjustment by continuously monitoring reception errors and adjusting the phase of the clock signal in real-time. The phase adjusting unit modifies the phase based on detected error patterns, transforming the static clock signal into a dynamically adaptable signal that optimizes transmission reliability while maintaining high speed.
Solution Approach 2:
The patent establishes a feedback loop where reception errors are detected and used to control phase adjustment. The determination unit identifies errors in received data, and this information feeds back to the phase adjusting unit, which modifies the clock signal phase accordingly. This closed-loop feedback mechanism enables the system to automatically compensate for phase shifts that cause reception errors at high transmission speeds.
2Measurement precision
If phase calibration is performed using multiple clock signals with different phases, then reception accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the phase calibration process into discrete steps using multiple clock signals with different phases (first clock signal with advanced phase, second clock signal with original phase, third clock signal with delayed phase). Each clock signal handles a specific phase range, dividing the complex calibration task into manageable segments that can be systematically tested and adjusted.
Solution Approach 2:
The patent changes the phase parameter of the clock signal to achieve calibration. By generating clock signals with different phase offsets and systematically adjusting the phase parameter based on reception results, the system achieves accurate phase alignment without requiring overly complex hardware, leveraging parameter variation as the primary calibration mechanism.
3Reliability
If the phase of the clock signal is adjusted to reduce reception errors, then transmission reliability is improved, but the complexity of control increases
Solution Approach 1:
The patent implements self-service control where the system automatically performs phase adjustment without external intervention. The determination unit autonomously detects reception errors and the phase adjusting unit automatically modifies the clock signal phase based on these detections. This self-contained control mechanism reduces the need for complex external control systems while maintaining high transmission reliability.
Solution Approach 2:
The patent uses feedback control where reception error information is fed back to automatically adjust the phase. The system monitors reception quality and dynamically adjusts the clock signal phase in response to detected errors, creating a self-regulating control loop that improves reliability without requiring complex manual control mechanisms.
Data Source
AI summary
A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.