Transmission Gate Body Effect Compensation Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional transmission gate circuits experience uneven turn-on resistance due to body effects, which degrade conductivity and slow operation, especially under varying input voltage conditions.
Innovation Solution
The proposed transmission gate circuit design includes specific coupling configurations between PMOS and NMOS devices, including bulk connections, to minimize the voltage difference between the source and body, thereby reducing body effects and maintaining consistent operation across a wide range of input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transmission gate circuit uses PMOS and NMOS devices with separate bulk connections, then the circuit can operate with standard MOS device structure, but body effect causes threshold voltage variation and uneven turn-on resistance
Solution Approach 1:
The patent merges the bulk connections of PMOS and NMOS devices by coupling the bulk of the first PMOS device to the bulk of the first NMOS device through additional PMOS and NMOS devices. This merging of previously separate bulk connections eliminates the body effect caused by voltage differences between sources and bulks, stabilizing threshold voltages while maintaining a manageable device structure.
Solution Approach 2:
The patent creates equipotential conditions between the bulk and source of MOS devices by ensuring that the bulk voltage tracks the source voltage through the coupling devices. This eliminates the voltage difference (VSB) that causes body effect, thereby stabilizing threshold voltages and ensuring uniform turn-on resistance across different input voltage conditions.
2Productivity
If body effect is present in MOS devices, then standard device structure can be used, but conductivity degrades and operation slows down
Solution Approach 1:
The patent converts the harmful body effect into a beneficial condition by using additional MOS devices to actively manage and equalize bulk voltages. The coupling devices utilize the same body effect mechanism to their advantage, ensuring that bulk voltages track source voltages, thereby eliminating threshold voltage variations and improving circuit operation speed.
3Adaptability or versatility
If PMOS and NMOS devices are used to stable turn-on resistor, then wide input voltage range is supported, but body effect causes uneven turn-on resistance under varying input voltages
Solution Approach 1:
The patent implements a feedback mechanism where the coupling PMOS and NMOS devices continuously monitor and adjust bulk voltages based on source voltage conditions. This feedback ensures that threshold voltages remain stable across wide input voltage ranges, maintaining uniform turn-on resistance despite variations in input voltage conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively compensates for body effects, ensuring consistent conductivity and operation by maintaining a near-zero voltage difference between the source and bulk of PMOS and NMOS devices, thus preventing degradation of circuit characteristics.
Implementation Method 1
a threshold voltage VTHp of the PMOS device P1 is as a function of VTHp=VTHp0+γ√|2ΦF+VSBp| and a threshold voltage VTHn of the NMOS device N1 is as a function of VTHn=VTHn0+γ√|2ΦF+VSBn| where VSB represents voltage difference between source and body
Data Source
AI summary
A transmission gate circuit includes a first PMOS device, a first NMOS device, a second PMOS device, a second NMOS device, and a third transistor. A gate electrode, a first electrode and a second electrode of the first PMOS device are coupled to a first control signal, an input end, and an output end, respectively. A gate electrode, a first electrode and a second electrode of the first NMOS device are coupled to a second control signal, the input end, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the second PMOS device are coupled to the first control signal, an input end, and a body electrode of the first PMOS device, respectively. A gate electrode, a first electrode, and a second electrode of the second NMOS device are coupled to the second control signal, a body electrode of the first PMOS device, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the third PMOS device are coupled to a second control signal, a first supply voltage, and the body electrode of the first PMOS device, respectively.


