Transmission Gate Cascode Protection for I/O Charge Injection
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Solution Overview
Problem
Integrated circuit devices face challenges in protecting I/O circuitry from charge injection and over/under voltage conditions due to increasing voltage requirements exceeding the capabilities of transmission gate transistors, particularly in process nodes below 10 nm.
Innovation Solution
Implementing a cascode structure with mid-node transistors and additional control signals to manage I/O pad voltages within safe limits, using a combination of PMOS and NMOS transistors to prevent damage from charge injection and maintain voltage within acceptable ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If I/O pads operate at higher voltages (1.8V) to meet external interface requirements, then compatibility with external components is improved, but transmission gate transistors with thick gate oxide (supporting only 1.5V) are damaged by overvoltage and charge injection
Solution Approach 1:
The patent introduces protection circuitry as an intermediary between the high-voltage I/O pads and the low-voltage transmission gate transistors. This protection circuitry includes voltage clamping elements and charge injection protection circuits that mediate the voltage levels, allowing the I/O pads to operate at 1.8V while preventing damage to the 1.5V transistors. The intermediary circuitry blocks harmful high-voltage transients and charge injection while passing normal operating signals.
Solution Approach 2:
The patent changes the voltage parameters of the transmission gate transistors by introducing dynamic voltage control. During I/O operations, the transistor gate voltages are dynamically adjusted to remain within safe limits (≤1.5V) even when I/O pads experience voltage overshoot or undershoot. This is achieved through control circuits that monitor I/O voltage levels and adjust transistor operating points accordingly, enabling the system to adapt to varying voltage conditions without damage.
2Productivity
If transmission gate transistors are used for I/O switching, then signal transmission capability is improved, but the transistors are vulnerable to charge injection damage from capacitive coupling during voltage transitions
Solution Approach 1:
The patent converts the harmful charge injection effect into a beneficial protective mechanism. The protection circuitry detects charge injection events (caused by capacitive coupling during voltage transitions) and activates protective elements that redirect or dissipate the injected charge safely. This transforms the potentially damaging charge injection into a controlled event that does not harm the transmission gate transistors, while maintaining their signal transmission functionality.
Solution Approach 2:
The patent implements preliminary protective measures before charge injection can damage the transistors. The protection circuitry is pre-configured with voltage clamping elements and charge redirection paths that are activated in advance or simultaneously with voltage transitions on I/O pads. This preliminary action prevents charge injection from accumulating to damaging levels in the transmission gate transistors, allowing safe operation during switching events.
Data Source
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AI summary
A transmission gate includes a first P-type transistor and a second P-type transistor coupled in series between a first signal node and an internal node. The transmission gate is enabled by turning on the first P-type transistor and the second P-type transistor to communicate signals between the first signal node and the internal node. The transmission gate is disabled by turning off the first P-type transistor and the second P-type transistor to stop communicating signals between the first signal node and the internal node. While the transmission gate is disabled, a third P-type transistor having a first current electrode coupled to a circuit node between the first and second P-type transistors and a control electrode coupled to the first signal node is used to track voltage of the first signal node and, in response to the tracking, control a voltage level at the circuit node to limit a gate-to-source voltage of the first P-type transistor.