Transmission Gate Layout Using Four Metal Zero Tracks
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in designing transmission gates with lower profiles that can be integrated into circuit layouts using fewer metal zero tracks, while maintaining effective current control and electrical connectivity between PMOS and NMOS transistors.
Innovation Solution
The design incorporates first and second PMOS transistors, first and second NMOS transistors, and conductive paths between their gates and source-drain terminals, with at least one conductive path including a segment perpendicular to metal zero segments, arranged using a total of four metal zero tracks, allowing for lower profile transmission gates and efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If transmission gates are designed with traditional configurations using more than four metal zero tracks, then electrical connectivity and current control are maintained, but profile height increases and integration efficiency decreases
Solution Approach 1:
The patent reconfigures the transmission gate layout by utilizing vertical stacking of metal zero tracks in the cross-section, transitioning from a planar arrangement to a three-dimensional structure. This allows four metal zero tracks to provide sufficient electrical connectivity and current control while reducing the horizontal profile height, thereby resolving the contradiction between compactness and functional complexity
Solution Approach 2:
The patent combines multiple functions into the four metal zero tracks by establishing conductive paths that connect gates and source-drain terminals of both PMOS and NMOS transistors through these tracks. This merging approach maintains all necessary electrical connections while minimizing the number of tracks required, thus reducing profile height without sacrificing functionality
2Productivity
If transmission gates use fewer metal zero tracks (four tracks), then profile height is reduced and integration is improved, but maintaining effective current control becomes more difficult
Solution Approach 1:
The patent applies local quality by creating specific conductive path configurations within the four metal zero tracks that are optimized for current control. The conductive paths are strategically arranged to ensure proper gate control and source-drain connectivity for both PMOS and NMOS transistors, maintaining current control effectiveness despite the reduced number of tracks
Solution Approach 2:
By utilizing the vertical dimension and cross-sectional arrangement of the four metal zero tracks, the patent creates multiple conductive paths that maintain effective current control. The three-dimensional configuration allows sufficient electrical connectivity without requiring additional horizontal tracks, thus improving integration efficiency while preserving reliability
Data Source
AI summary
A method of manufacturing a transmission gate includes overlying a first active area with a first metal zero segment, the first active area including first and second PMOS transistors, overlying a second active area with a second metal zero segment, the second active area including first and second NMOS transistors, and configuring the first and second PMOS transistors and the first and second NMOS transistors as a transmission gate by forming three conductive paths. At least one of the conductive paths includes a first conductive segment perpendicular to the first and second metal zero segments, and the first and second metal zero segments have a first offset distance corresponding to three times a metal zero pitch.