Electro-Optical Device Transmission-Gate Layout for Display Uniformity
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Solution Overview
Problem
In electro-optical devices with parallel P-channel and N-channel transistors, non-uniform transistor characteristics lead to display unevenness and hinder device downsizing due to wasted space when adjusting transistor sizes to match characteristics.
Innovation Solution
The electro-optical device employs data lines grouped into sets, with transmission gates having transistors of different channel lengths arranged in a specific order to ensure uniform transistor characteristics and reduce pitch, using a transmission gate structure with complementary P-channel and N-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistor sizes are adjusted to make characteristics uniform, then display uniformity is improved, but device area increases and array pitch cannot be narrowed
Solution Approach 1:
The patent changes the channel length parameter of transistors to achieve uniform characteristics. Specifically, transistors in even-numbered data line groups have a channel length of L, while transistors in odd-numbered data line groups have a channel length of L/2. This parameter variation compensates for systematic characteristic differences between adjacent data lines, achieving display uniformity without increasing device area or array pitch.
2Manufacturing precision
If transistor sizes are adjusted to make characteristics uniform, then display uniformity is improved, but array pitch cannot be narrowed
Solution Approach 1:
The patent applies parameter changes by varying the channel length of transistors based on their position in the data line group. Even-numbered groups use channel length L while odd-numbered groups use channel length L/2. This allows uniform display characteristics to be achieved within the same array pitch, eliminating the need to increase pitch for transistor size adjustment.
3Speed
If P-channel and N-channel transistors are arranged in parallel, then writing speed is improved, but display unevenness occurs due to non-uniform characteristics
Solution Approach 1:
The patent maintains the parallel P-channel and N-channel transistor configuration for high writing speed while introducing channel length variation to achieve uniformity. By setting different channel lengths (L for even groups, L/2 for odd groups), the patent compensates for systematic characteristic differences, achieving both fast writing speed and uniform display without sacrificing either performance.
Data Source
AI summary
When data lines are arrayed along an X direction, a transistor P1 of a transmission gate corresponding to the data line in a given column is adjacent, in the X direction, to a transistor N1 of the transmission gate corresponding to the data line adjacent to the data line in the given column, and the transistor N1 of the transmission gate corresponding to the data line in the given column is adjacent, in the X direction, to the transistor P1 of the transmission gate corresponding to the data line adjacent to the data line in the given column.