Transmission Gate Layout With Perpendicular Routing on Four M0 Tracks
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in designing transmission gates with lower profiles that can be integrated into circuit layouts using fewer metal zero tracks, while maintaining effective current control and electrical connectivity between PMOS and NMOS transistors.
Innovation Solution
The design incorporates first and second PMOS transistors, first and second NMOS transistors, and conductive paths between their gates and source-drain terminals, with at least one conductive path including a segment perpendicular to the metal zero segments, arranged using a total of four metal zero tracks, allowing for lower profile transmission gates and efficient integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If transmission gates are designed with traditional layouts using more than four metal zero tracks, then electrical connectivity and current control are maintained, but the profile height and layout complexity increase
Solution Approach 1:
The patent reconfigures the transmission gate layout by utilizing vertical conductive paths that extend perpendicular to the metal zero segments, effectively using the vertical dimension to reduce the horizontal footprint and profile height while maintaining all necessary electrical connections between PMOS and NMOS transistors
Solution Approach 2:
The patent merges the gate control paths and source-drain connections into a unified layout structure that shares common metal zero tracks, reducing the total number of required metal zero tracks to just four while maintaining proper electrical isolation and connectivity between all transistor components
2Area of stationary object
If transmission gates are compacted to reduce profile, then integration density improves, but electrical connectivity between transistors may be compromised
Solution Approach 1:
The patent segments the conductive paths into distinct vertical and horizontal portions, with vertical segments providing compact routing between metal layers and horizontal segments ensuring proper electrical connectivity, allowing the gate to achieve reduced footprint while maintaining reliable electrical pathways between all transistor terminals
Solution Approach 2:
The patent introduces intermediate conductive structures that mediate between the compacted transistor layouts and the metal zero tracks, ensuring that even as the overall profile is reduced, proper electrical connectivity is maintained through these intermediary conductive elements
Data Source
AI summary
A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.