Transmission-Line TDC Architecture for Sub-100 fs Phase Resolution
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) face challenges in achieving sub-picosecond or femtosecond-level resolution while maintaining good linearity, due to limitations in CMOS processes and sensitivity to PVT variations, which affect the performance of all-digital phase-locked loops (ADPLLs) in digital RF transceivers.
Innovation Solution
A three-stage time-to-digital converter design utilizing a transmission line structure, comprising a single-chain delay TDC, Vernier delay chain TDC, and Vernier transmission line TDC, with parallel connection and adaptive locking detectors, employs CMOS inverters, comparators, and transmission lines to achieve sub-100 fs resolution and reduce sensitivity to PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CMOS process is used for TDC, then manufacturing simplicity is maintained, but resolution cannot achieve sub-100 fs level
Solution Approach 1:
The patent replaces conventional CMOS delay-based timing mechanisms with a transmission line structure that uses electromagnetic wave propagation. The transmission line's distributed capacitance and inductance create precise time delays through electromagnetic field interactions rather than relying on CMOS transistor switching delays, enabling sub-100 fs resolution that overcomes CMOS process limitations.
Solution Approach 2:
The patent changes the fundamental operating parameter from CMOS switching time constants to transmission line propagation characteristics. By utilizing the transmission line's characteristic impedance, propagation velocity, and distributed LC parameters, the system achieves timing resolution determined by electromagnetic wave propagation rather than transistor switching speeds, thereby achieving sub-100 fs resolution.
2Measurement precision
If Vernier delay chain structure is used to improve resolution, then dynamic range increases, but power consumption and layout area increase significantly
Solution Approach 1:
The patent extracts the timing measurement function from the complex Vernier delay chain structure and implements it using a simplified transmission line structure. The transmission line directly provides the necessary time delays through its physical dimensions and electromagnetic properties, eliminating the need for multiple cascaded delay units and their associated power consumption and area requirements.
Solution Approach 2:
The patent uses the transmission line's natural electromagnetic propagation characteristics to replicate the timing delay function that would otherwise require complex Vernier delay chains. The transmission line effectively 'copies' the time-delay functionality in a more efficient physical form, achieving the same measurement precision with reduced power and area.
3Measurement precision
If Vernier delay chain structure is used to improve resolution, then dynamic range increases, but layout area increases significantly
Solution Approach 1:
The patent replaces the mechanical/circuit-based Vernier delay chain with an electromagnetic field-based transmission line structure. The transmission line's distributed capacitance and inductance create the necessary time delays through electromagnetic wave propagation, achieving high resolution with a compact layout that does not require the extensive area of cascaded delay units.
Solution Approach 2:
The patent changes the physical implementation from discrete CMOS delay units to a continuous transmission line structure. By adjusting the transmission line's physical dimensions, dielectric properties, and conductor geometry, the system achieves precise time delays in a compact form factor, reducing layout area while maintaining high resolution.
4Productivity
If analog TDC structure is used, then conversion speed is slow and stability is low, but structure complexity is reduced for integration
Solution Approach 1:
The patent replaces analog voltage-based timing with electromagnetic wave propagation in a transmission line. The transmission line's distributed LC parameters create stable, predictable time delays that are inherently resistant to PVT variations, while the digital readout mechanism ensures fast conversion speed and high stability simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves ultra-high resolution and low in-band phase noise, suitable for 5G and 6G communication systems, with improved linearity and reduced power consumption, complexity, and sensitivity to PVT variations.
Implementation Method 1
a first transmission line structure and a second transmission line structure... the first clock signal is input to an input end of the first transmission line structure, and the second clock signal is input to an input end of the second transmission line structure
Data Source
AI summary
A time-to-digital converter with a sub-100 fs resolution and based on a transmission line structure includes three-stage of time-to-digital converters (TDCs), where the three-stage of TDCs are connected in parallel; and a plurality of delay units are disposed for each stage of TDC, the delay unit is connected to a locking detector, and the locking detector determines an output result of each stage TDC and performs locking; two input signals first enter the first-stage TDC for being quantized, and based on an output result of a comparator, the locking detector determines that the first-stage TDC has been locked, and an output thereof is frozen; and determining TDC at the next stage is performed, and a phase difference between the two signals gradually decreases with the locking of a phase-locked loop, which means phase difference alignment is performed, and the phase-locked loop completes locking.