Transmission Apparatus Priority Control via Token Bucket Shaping
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Solution Overview
Problem
Current transmission apparatuses face challenges in implementing priority control of arbitrary priority classes due to hardware constraints, particularly in managing packet processing rates exceeding 100 Gbps, where software schedulers struggle to efficiently handle diverse data types with varying delay requirements.
Innovation Solution
The transmission apparatus incorporates a CPU and FPGA configuration that uses a token bucket method for bandwidth control, allowing flexible adjustment of shaping rates and output patterns to cope with priority class variations, while minimizing conflicts and displacements in token addition timings through magnification controlling units and timer monitoring processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software schedulers are used to control packet processing, then flexibility in handling diverse data types with varying delay requirements is improved, but processing speed deteriorates when exceeding 100 Gbps
Solution Approach 1:
The system divides the transmission apparatus into distinct functional units: hardware input processing unit for packet intake, hardware queue management unit for buffering, hardware output processing unit for transmission, and software scheduler for control. This segmentation allows hardware to handle high-speed packet processing while software provides flexible scheduling decisions, resolving the contradiction between speed and adaptability.
Solution Approach 2:
The patent introduces a hardware queue management unit as an intermediary between the high-speed hardware input/output processing units and the software scheduler. This intermediary buffer allows the software scheduler to make flexible scheduling decisions without becoming a bottleneck, as packets can be queued in hardware while waiting for software scheduling decisions, thus maintaining both high speed and adaptability.
2Speed
If hardware is used for input and output processing, then packet processing speed is improved, but ability to implement arbitrary priority classes deteriorates due to hardware constraints
Solution Approach 1:
The queue management unit implements dynamic priority control where the readout allowable amount (credit) assigned to each queue can be flexibly adjusted based on priority degree. This dynamic allocation allows arbitrary priority classes to be implemented in hardware without sacrificing processing speed, as the credit values can be modified to reflect changing priority requirements while maintaining high-speed hardware operation.
3Adaptability or versatility
If multiple queues are managed with individual shapers, then priority control capability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple individual shaper functions into a single queue management unit that handles multiple queues. Instead of having separate shaper hardware for each queue, the unified queue management unit manages multiple queues with a single credit-based control mechanism. This merging reduces device complexity while maintaining priority control capability through the scheduler's ability to allocate different readout allowable amounts to different queues based on their priority degrees.
Data Source
AI summary
There is provided a transmission apparatus including at least one memory in which a first data including a first destination information and a second data including a second destination information are stored, and at least one processor coupled to the at least one memory and the at least one processor configured to control the at least one memory to output the first data and the second data stored in the at least one memory according to a set rate, and control the set rate to output one of the first data and the second data according to a priority degree.