Differential Transmit Driver Circuit for Stable Output Impedance
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Solution Overview
Problem
Classical current mode logic (CML) type driver circuits face limitations in maintaining constant output impedance and suffer from data-dependent modulation of the reflection coefficient due to asymmetrical capacitance and impedance, leading to reduced insertion and increased cross-talk at high data rates.
Innovation Solution
A driver circuit with separate current limiting devices in each differential leg and a center-tapped inductor configuration is used to maintain output impedance and reduce parasitic capacitance effects, allowing for improved return-loss performance and reduced supply voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a classical CML driver stage with resistive load is used, then the circuit structure is simple, but the output impedance cannot be maintained constant and becomes data-dependent
Solution Approach 1:
The patent segments the capacitance contributors at the output node into separate components that can be independently compensated. By dividing the total output capacitance into distinct parts (transistor drain capacitance, interconnect capacitance, load capacitance), the design can apply targeted inductive compensation to each segment, maintaining constant output impedance across different output states.
Solution Approach 2:
The patent introduces inductors as intermediary elements to compensate for parasitic capacitances. These inductors act as mediators between the capacitance contributors and the transmission line, providing impedance transformation and matching that maintains constant output impedance regardless of the output state. The inductors serve as intermediate components that decouple the capacitance variations from the output impedance.
2Adaptability or versatility
If inductors are used to compensate parasitic capacitances, then impedance matching bandwidth is improved, but device complexity increases
Solution Approach 1:
The patent designs the inductor network to serve multiple functions simultaneously: impedance matching, parasitic capacitance compensation, and bandwidth extension. The same inductive elements that provide impedance transformation also compensate for the capacitive effects of the transistor outputs and interconnects, eliminating the need for separate compensation circuits and reducing overall device complexity.
Solution Approach 2:
The patent merges the impedance matching network with the parasitic capacitance compensation function into a single integrated inductor structure. Rather than using separate components for each function, the design combines these roles into unified inductive elements that perform both tasks, thereby improving bandwidth while minimizing the increase in device complexity.
3Use of energy by moving object
If supply voltage is reduced to match CMOS logic domain, then power consumption is reduced, but headroom for achieving specified output swing is limited
Solution Approach 1:
The patent changes the impedance parameters of the driver circuit by introducing inductive elements that transform the effective output impedance. This impedance transformation allows the circuit to achieve the required 1 Vppd output swing with reduced supply voltage by optimizing the voltage transfer efficiency and reducing the voltage headroom requirements through improved impedance matching.
Data Source
AI summary
A driver circuit includes a differential input, a differential output, a bias node, a first T-coil having a first node coupled to the negative output node and a second node coupled to a source of supply voltage, a second T-coil having a first node coupled to the positive output node and a second node coupled to the source of supply voltage, a first transistor having a current path coupled between the center tap of the first T-coil and a first intermediate node, a second transistor having a current path coupled between the center tap of the second T-coil and a second intermediate node, a third transistor having a current path coupled between the first intermediate node and ground, and a fourth transistor having a current path coupled between the second intermediate node and ground.