Transmit Clock Phase Trimming for Deterministic Jitter Reduction
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Solution Overview
Problem
High-speed data transmission circuits face issues with deterministic jitter due to phase mismatches in clock signals, leading to timing variations and degradation of timing margins in output data signals.
Innovation Solution
A data transmission circuit that includes phase adjustment circuits and a timing measurement circuit to adjust clock signals based on measured timing parameters, such as edge times, to reduce mismatches and jitter in output data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase adjustment circuits are added to correct clock signal mismatches, then deterministic jitter is reduced, but device complexity increases
Solution Approach 1:
The patent implements feedback by measuring actual clock signal phase relationships and using this information to adjust phase shifters. The timing measurement circuit continuously monitors clock phases and feeds this data back to control logic, which then modifies the phase shift amounts to maintain optimal timing relationships, thereby reducing deterministic jitter through closed-loop control
Solution Approach 2:
The patent changes the phase parameter of clock signals dynamically using controllable phase shifters. By adjusting the phase shift amount based on measured timing relationships, the system optimizes clock signal timing to compensate for mismatches in the data path, directly addressing deterministic jitter through parameter optimization
2Measurement precision
If timing measurement circuits are implemented to monitor edge times, then timing margin accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The system performs self-diagnosis and self-adjustment by using its own output signals to measure timing relationships. The timing measurement circuit uses the actual data signals and clock signals passing through the system to determine phase relationships, eliminating the need for external test equipment and enabling automated calibration that compensates for manufacturing variations
3Reliability
If multiple phase adjustment circuits are used for different clock signals, then timing variations are reduced, but ease of manufacture decreases
Solution Approach 1:
The patent employs a universal phase adjustment approach where controllable phase shifters are used across multiple clock signal paths. The same type of phase shifter circuit is reused for different clock signals (e.g., phi0, phi1, phi2, phi3), allowing standardized manufacturing processes and simplifying assembly while maintaining the ability to independently adjust each clock phase to reduce timing variations
Data Source
AI summary
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.