Transmit Timestamp Autocalibration for High-Speed Ethernet

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Solution Overview

Problem

Existing methods for inserting timestamps in transmitted data suffer from variable latency due to clock domain crossings in PCS and FEC processing blocks, leading to inconsistent timestamps, especially in high-speed networks like 100 GB Ethernet, resulting in excessive jitter.

Innovation Solution

A method and system for transmit timestamp autocalibration, which generates a calibration pulse, samples the latency in the transmit data pipeline, and adjusts the timestamps based on measured latency to ensure consistent timestamp insertion across packets and device startups, using a calibration pulse generator, timestamp sampler, and timestamp adjuster.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If timestamps are inserted into transmitted data packets, then network timing measurement capability is improved, but timestamp consistency deteriorates due to variable latency from clock domain crossings in PCS and FEC processing blocks

Engineering Contradiction:

Improvenetwork timing measurement capabilityVSAvoidtimestamp consistency

Core Design Contradiction:

Measurement precisionVSStability of the object's composition

Solution Approach 1:

The system performs preliminary calibration by inserting calibration packets with known timestamps before normal data transmission. These calibration packets traverse the same processing pipeline (PCS, FEC, clock domain crossings) as normal packets, allowing the system to pre-measure and store the actual latency experienced. This preliminary measurement enables subsequent compensation for timestamp variations without affecting real-time data transmission consistency.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system measures the latency introduced by processing blocks using calibration packets and uses this measured latency information to adjust compensation values for timestamp accuracy. The feedback loop continuously monitors latency variations from clock domain crossings and adjusts the timestamp compensation accordingly, ensuring consistent timing measurements despite pipeline variations.

Inventive Principle:

Principle #23Feedback

2Speed

If high-speed network transmission is implemented (e.g., 100 GB Ethernet), then transmission speed is improved, but timestamp jitter increases due to short clock periods (6.7 nanoseconds) magnifying latency variance

Engineering Contradiction:

Improvetransmission speedVSAvoidtimestamp jitter

Core Design Contradiction:

SpeedVSStability of the object's composition

Solution Approach 1:

The system replaces direct hardware timestamp insertion with a software-based compensation mechanism. Instead of relying solely on hardware timestamp generators that are subject to clock domain crossing variations, the system uses measured latency data to calculate and apply software compensation values to timestamps, effectively substituting mechanical/hardware timing with a more flexible software-based correction approach.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system dynamically adjusts timestamp parameters by applying compensation values based on measured latency. The compensation values are calculated as the difference between expected and actual latency, and these parameter adjustments are applied to correct timestamp values inserted into transmitted packets, thereby reducing jitter at high transmission speeds.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If variable latency occurs from clock domain crossings in PCS and FEC blocks, then device functionality is improved, but timestamp accuracy deteriorates due to inconsistent delay between timestamp insertion and packet transmission

Engineering Contradiction:

Improvedevice functionalityVSAvoidtimestamp accuracy

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The system introduces calibration packets as intermediary elements that carry known timestamp information through the processing pipeline. These calibration packets serve as mediators to measure the actual latency introduced by PCS, FEC, and clock domain crossings. The measured latency from these intermediary calibration packets is then used to adjust timestamps in normal data packets, decoupling the device's adaptive processing from timestamp accuracy requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10686581B2Methods, systems, and computer readable media for transmit timestamp autocalibration

Publication Date: 2020.06.16 KEYSIGHT TECHNOLOGIES INC

AI summary

A method for transmit timestamp autocalibration includes generating a calibration pulse for calibrating a transmit timestamp in a transmitting device. The method further includes applying the calibration pulse to a transmit data pipeline in the transmitting device. The method further includes sampling a transmit timestamp when the calibration pulse reaches a timestamp sample triggering location in the transmit data pipeline upstream from an egress point of the transmitting device. The method further includes measuring a latency between a time that the calibration pulse reaches the timestamp sample triggering location and a time that the calibration pulse reaches a location downstream from the timestamp sample triggering location. The method further includes generating an adjusted timestamp based on the measured latency and inserting the adjusted timestamp into a data packet to be transmitted from the transmitting device.