Transmitter Bias Equalization for Low-Power Serial Links
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Solution Overview
Problem
Conventional transmitter equalization methods result in high power consumption and poor equalization performance, especially when dealing with high-speed serial links and direct-current signals, due to the need for multiple high-speed nets and sensitivity to timing shifts.
Innovation Solution
The implementation of a current-mode transmitter driver with a driver bias circuit that boosts the bias level on a common net in response to data transitions, rather than on the differential output terminals, reducing the number of equalization nodes and minimizing power consumption while maintaining effective equalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If equalization is arranged on the output of the transmitter driver with multiple driver slices, then high frequency transitions are emphasized to cope with transmission loss, but power consumption increases significantly
Solution Approach 1:
The patent extracts the equalization function from the differential output path and relocates it to the common net path. By taking out the equalization operation from the high-speed differential signals and applying it only to the common net, the invention reduces the number of nodes requiring equalization while maintaining the equalization effect, thereby reducing power consumption.
Solution Approach 2:
Instead of applying equalization to the differential outputs as in conventional designs, the patent inverts the approach by applying equalization to the common net before the differential split. This inversion allows equalization to be performed on a single net rather than multiple differential nets, reducing the overall power consumption while maintaining equalization performance.
2Adaptability or versatility
If timing shift is applied to post-cursor slices, then equalization can be adjusted, but equalization performance deteriorates
Solution Approach 1:
The patent introduces the common net as an intermediary path for equalization. By performing equalization on the common net rather than directly on the differential output paths, the invention creates a stable intermediate stage that is less sensitive to timing shifts, thereby maintaining equalization performance while preserving adjustability.
3Productivity
If all nets including pre-cursor, main-cursor, and post-cursor driver slices operate at high speed, then data transmission is achieved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating the operational requirements of different nets. The differential output nets maintain high-speed operation for data transmission, while the common net operates at a lower speed for equalization purposes. This localized differentiation of operational characteristics reduces overall power consumption while maintaining data transmission capability.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A transmitter with low power and high accuracy equalization is shown. The transmitter includes a transmitter driver and a driver bias circuit. The transmitter driver receives data, and generates a positive differential output and a negative differential output to be transmitted by the transmitter. The driver bias circuit is coupled to the transmitter driver to bias the transmitter driver, wherein the driver bias circuit is configured to boost the bias level of the transmitter driver in response to transitions of the data.