High-Speed Link Transmitter Calibration for Clock and Data DCD
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Solution Overview
Problem
Conventional high-speed data communications links suffer from duty cycle distortion (DCD) in both the clock and data paths, leading to deterministic jitter and degraded performance, as existing correction schemes only address clock DCD and neglect residual data DCD in the open loop data path.
Innovation Solution
An integrated circuit with a clock and data duty cycle distortion calibration circuit that monitors transmit output data to generate correction signals for both clock and data paths, adjusting the transmitter to correct duty cycle distortions and ensure balanced rise and fall times, thereby improving link performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional duty cycle correction schemes are implemented in the transmitter design, then clock duty cycle distortion is corrected, but residual data duty cycle distortion remains uncorrected leading to deterministic jitter
Solution Approach 1:
The patent implements a feedback mechanism where the transmitter monitors its own output data and uses this information to generate correction signals. The monitor circuit detects duty cycle distortion in the output data, and the control circuit adjusts the clock signal or data signal based on this feedback to eliminate the distortion, creating a closed-loop correction system that continuously maintains optimal performance
Solution Approach 2:
The patent introduces an intermediary control circuit that acts as a mediator between the monitor circuit and the signal generation components. This control circuit processes the monitoring information and generates appropriate correction signals that adjust either the clock signal parameters or data signal characteristics, serving as an intermediate element that translates detection into corrective action
2Productivity
If a half-rate clocking system is used to transmit serial data, then data transmission is achieved, but non-ideal clock duty cycle causes output data distortion
Solution Approach 1:
The patent dynamically changes the parameters of the clock signal or data signal based on detected distortion. The system adjusts clock duty cycle, phase, or data signal characteristics in real-time to compensate for distortions, allowing the system to maintain high transmission rates while correcting output quality through continuous parameter optimization
Solution Approach 2:
The patent transforms the static clocking system into a dynamic one where the clock signal parameters or data signal characteristics can be adjusted in real-time. The monitor and control circuits enable continuous adaptation of signal parameters to maintain optimal performance despite variations in operating conditions or component tolerances
3Manufacturing precision
If transmitter clock exhibits ideal 50% duty cycle, then clock-related distortion is minimized, but unbalanced rise and fall times in data path still cause output distortion
Solution Approach 1:
The patent separates the correction function into distinct segments: one that handles clock signal correction and another that handles data signal correction. The control circuit can independently adjust clock parameters or data path characteristics based on which path is causing the distortion, allowing targeted correction of specific impairment sources without affecting other aspects of the system
Data Source
AI summary
An integrated circuit having a transmitter is provided. The transmitter may include a serializer, a driver, and an associated calibration circuit. The calibration circuit may include a detector and a control circuit. The control circuit may output a first control signal for selectively configuring the serializer to inject test data and may also output a second control signal for selectively inverting the input polarity of the detector. The control circuit may configure the transmitter in at least four different modes by adjusting the first and second control signals. In each of the four modes, the control circuit may sweep a clock duty cycle correction (DCC) setting that controls only the serializer until the detector flips. Codes generated in this way may be used to compute calibrated settings that mitigates both clock and data duty cycle distortion for the transmitted data.