Transmitter Delay Mismatch Compensation via Tunable All-Pass Filter

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Solution Overview

Problem

Existing transmitter devices face challenges in compensating for delay mismatches in their analog parts, which lead to distortion and affect signal quality, particularly in GSM/EDGE systems, where existing solutions either require tight component variations difficult to achieve in mass production or lack compensation for delay mismatches.

Innovation Solution

A transmitter device with a digital and analog part, incorporating a digital modulator, digital-to-analog converters, and filter units that store compensation filter values to adjust for delay mismatches, using a first-order all-pass filter with a tunable pole and zero constellation to compensate for delay mismatches in the analog part.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If tight component variations are designed to fulfill delay mismatch limits, then signal quality is improved, but manufacturing difficulty increases

Engineering Contradiction:
Improvesignal qualityVSAvoidmanufacturing difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing compensation filter values in a table during the design phase. These values are determined based on expected delay mismatches and are readily available during mass production, eliminating the need for complex real-time calculations or tight component tolerances.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameter of filter values dynamically based on the determined delay mismatch. By adjusting the filter values selected from pre-stored compensation values, the system compensates for delay mismatches without requiring tight component variations, thus resolving the contradiction between signal quality and manufacturing ease.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If complex compensation methods are used to correct delay mismatch, then signal quality is improved, but device complexity increases

Engineering Contradiction:
Improvesignal qualityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent pre-calculates compensation filter values for various delay mismatch scenarios and stores them in a table. During operation, the system only needs to determine the actual delay mismatch and select the appropriate pre-computed values, avoiding complex real-time compensation calculations and reducing device complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a table to store copies of pre-computed compensation filter values. Instead of performing complex calculations during operation, the system copies the appropriate pre-stored values into the filter units, significantly simplifying the device architecture while maintaining compensation effectiveness.

Inventive Principle:
Principle #26Copying

3Reliability

If delay mismatch compensation is implemented, then image rejection is improved, but filter adjustment complexity increases

Engineering Contradiction:
Improveimage rejectionVSAvoidfilter adjustment complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent pre-determines and stores compensation filter values for various delay mismatch conditions. The system automatically selects and applies the appropriate pre-stored values based on the measured delay mismatch, eliminating the need for manual filter adjustment and simplifying operation while maintaining image rejection performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP2002632B1Delay Mismatch Compensation Using a Low Complexity Structure in Signal Transmitters with Digital and Analog Components
Publication Date: 2015.10.21 NXP BV
  • EP2002632B1 patent drawingFigure 1
  • EP2002632B1 patent drawingFigure 2
  • EP2002632B1 patent drawingFigure 3

AI summary

A transmitter device is provided which comprises a digital part (DP) and an analog part (AP). The transmitter device furthermore comprises a digital modulator (DM) in the digital part (DP) for receiving bits (MB) and for digitally modulating the receiving bits (MB). A first (IDAC; RDAC) and second digital-to-analog converter (QDAC; ODAC) are provided. The transmitter device furthermore comprises at least one filter unit (H1; HQ; Hl) which is arranged in the digital part (DP) and which is coupled between the first and/or second digital-to-analog converter (IDAC; QDAC) and the digital modulator (DM). A table unit (TU) is coupled to the at least one filter unit (H1; HQ) and is used to store pre- defined compensation filter values for the at least one filter unit (H1; HQ) which are required to compensate different delay mismatches in the analog part (AP) of the transmit¬ ter device. The filter values of the at least one filter unit (H1; HQ) are set to those compensa¬ tion filter values as stored in the table unit (TU) which correspond to a determined delay mismatch.