Multi-Level Transmitter Edge Adjustment for Switching Jitter

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Solution Overview

Problem

As the number of levels in multi-level signaling increases, switching jitter also increases, leading to a decrease in horizontal eye opening and timing margin.

Innovation Solution

A transmitter and transceiver system that includes an encoder, an edge adjustment circuit, and a driver circuit. The edge adjustment circuit adjusts the falling edge timing of the encoded signal corresponding to the most significant bit and the rising edge timing of the encoded signal corresponding to the least significant bit, thereby reducing switching jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If multi-level signaling with increased number of levels is used to transmit more information, then information transmission capacity is improved, but switching jitter increases and timing margin decreases

Engineering Contradiction:
Improveinformation transmission capacityVSAvoidtiming margin
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The encoded signal is divided into multiple bits, with different edge adjustment circuits applied to different bit positions. The most significant bit and least significant bit receive opposite polarity adjustments, while intermediate bits receive proportional adjustments based on their position, allowing independent optimization of each bit's timing characteristics

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different edge adjustment amounts are applied to different bits based on their significance. The most significant bit receives a full adjustment amount in one direction, intermediate bits receive proportional adjustments, and the least significant bit receives a full adjustment amount in the opposite direction, creating locally optimized timing characteristics for each bit position

Inventive Principle:
Principle #3Local quality

2Loss of information

If multi-level signaling with increased number of levels is used to transmit more information, then information transmission capacity is improved, but switching jitter increases

Engineering Contradiction:
Improveinformation transmission capacityVSAvoidswitching jitter
Core Design Contradiction:
Loss of informationVSObject-affected harmful factors

Solution Approach 1:

The edge adjustment circuit proactively compensates for expected switching jitter by pre-adjusting the timing of encoded signal edges. By applying opposite polarity adjustments to most significant and least significant bits, and proportional adjustments to intermediate bits, the system counteracts the jitter that would otherwise occur during multi-level transitions

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The timing adjustment is performed in advance on the encoded signals before they are transmitted through the channel. The edge adjustment circuit modifies the rising and falling edge timings of each bit based on its significance, preparing the signal to maintain better timing characteristics despite the increased transitions inherent in multi-level signaling

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4518263A1Transmitter and transceiver for switching jitter improvement
Publication Date: 2025.03.05 SAMSUNG ELECTRONICS CO LTD
  • EP4518263A1 patent drawingFigure 1
  • EP4518263A1 patent drawingFigure 2
  • EP4518263A1 patent drawingFigure 3

AI summary

Disclosed are a transmitter and transceiver for improving switching jitter. The transmitter includes an encoder that encodes an input signal representable by x levels (where x is a natural number of 3 or more) and outputs a plurality of encoded signals representing a multi-bit binary number including a most significant bit and a least significant bit; an edge adjustment circuit that generates a plurality of adjusted encoded signals by adjusting a falling edge timing of a first one of the encoded signals corresponding to the most significant bit and adjusting a rising edge timing of a second one of the encoded signals corresponding to the least significant bit; and a driver circuit that generates and outputs an output signal having the x levels based on the adjusted encoded signals.