Transmitter Multiplexing Byte Enable on Data Bus
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Solution Overview
Problem
Conventional data bus systems require a separate byte enable bus to facilitate partial write operations, leading to an increase in the number of bits transmitted, which can be inefficient in terms of signal or pin usage without compromising transmission bandwidth.
Innovation Solution
The proposed solution involves transmitting byte enable information over the data bus instead of the byte enable bus, using a transmitter with an input data buffer, multiplexer circuitry, and an output buffer to multiplex valid bytes and byte enable information, reducing the overall bits transmitted by removing invalid bytes and encoding this information within the data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate byte enable bus is used to facilitate partial write operations, then partial write capability is improved, but the number of bits transmitted increases
Solution Approach 1:
The patent merges the byte enable information transmission with the data bus by multiplexing byte enable bits onto data bus lines. Instead of using a separate byte enable bus, the system combines data and byte enable information into a single transmission medium, thereby reducing the total number of bits transmitted while maintaining partial write capability
Solution Approach 2:
The data bus is given multiple functions: it transmits both data bytes and byte enable information. By making the data bus universal for both purposes, the system eliminates the need for a dedicated byte enable bus, reducing overall signal count while preserving functionality
2Device complexity
If the number of signals or pins is reduced, then system architecture is optimized, but transmission bandwidth may be compromised
Solution Approach 1:
The system dynamically multiplexes different types of information (data bytes and byte enable bits) onto the same bus at different times within the same transmission cycle. This dynamic time-division multiplexing allows the data bus to carry both data and control information without compromising bandwidth, as the total transmission capacity is fully utilized
Solution Approach 2:
The transmission protocol uses periodic time slots within each data transmission cycle to alternate between transmitting data bytes and byte enable information. This periodic multiplexing ensures that both data and control signals are transmitted systematically without losing bandwidth efficiency
Data Source
AI summary
A transmitter comprising an input data buffer to store a plurality of bytes received on a first interconnect; multiplexer circuitry coupled to the input data buffer; and an output buffer coupled to the multiplexer circuitry, a second interconnect, and a third interconnect. The multiplexer circuitry is to: receive byte enable information in the input data buffer; determine that one or more of the plurality of bytes stored in the input data buffer are invalid; store an indicator in the output buffer; store valid bytes of the plurality of bytes in the output buffer to transmit on the third interconnect; and store the byte enable information in the output buffer to transmit on the third interconnect.