Transmitter Selective Delay for ISI and SSO Compensation
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Solution Overview
Problem
Existing channel compensation techniques, such as pre-emphasis and equalization methods, are limited in effectively addressing intersymbol interference (ISI) and simultaneous switching outputs (SSO) in high-speed digital communication systems, particularly in parallel data buses with source synchronous clocking, leading to reduced data rate and reliability.
Innovation Solution
The implementation of transmitter-based techniques using selective pulse width modulation to detect predefined signal corruption conditions, applying a reduced delay to signals anticipated to exhibit ISI and SSO, thereby compensating for these distortions by shifting the phase of digital data in the time domain before the analog output driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional pre-emphasis techniques are used to compensate for channel distortions, then intersymbol interference is partially mitigated, but simultaneous switching outputs effects remain unaddressed and device complexity increases
Solution Approach 1:
The transmitter circuit is segmented into multiple independent delay elements, each associated with a specific signal path. This allows selective application of delay compensation to individual signals that are susceptible to ISI or SSO, rather than applying complex compensation to all signals. The segmentation enables targeted intervention while keeping the overall system relatively simple.
Solution Approach 2:
Different delay compensation strategies are applied to different signal paths based on local conditions. The system detects which specific signals are experiencing ISI or SSO and applies reduced delay selectively to those signals, while leaving other signals with nominal delay. This local quality approach optimizes compensation effectiveness while minimizing unnecessary complexity.
2Reliability
If equalization techniques are employed in the receiver to remove intersymbol interference, then data recovery is improved, but the setup and hold margin is reduced limiting data rate
Solution Approach 1:
The system performs preliminary compensation action at the transmitter by detecting anticipated ISI and SSO conditions and applying reduced delay to affected signals before they are transmitted. This preliminary action prevents the degradation of setup and hold margins at the receiver, allowing the system to achieve both high data rates and reliable data recovery without requiring aggressive equalization that would limit productivity.
3Reliability
If pre-emphasis techniques change drive strength within a pulse to correct ISI, then serial interference is compensated, but parallel SSO effects are not resolved and manufacturing precision becomes difficult
Solution Approach 1:
The system changes the delay parameter selectively for different signal paths based on detected corruption conditions. By using discrete delay elements with different delay values, the system can adjust the timing parameter of individual signals to compensate for both ISI and SSO effects. This parameter-based approach is more manufacturable than analog drive strength adjustment, as it uses digital delay elements that are easier to design across wide process, voltage, and temperature variations.
Data Source
AI summary
Transmitter-based techniques are provided for compensation of intersymbol interference and/or simultaneous switching outputs, using selective pulse width modulation. One or more signals are transmitted by detecting whether one or more of said signals satisfy one or more predefined signal corruption conditions, wherein said predefined signal corruption conditions indicate that one or more of said signals are anticipated to exhibit one or more of intersymbol interference and simultaneous switching outputs; and selecting a delay for one or more of the signals based on the one or more predefined signal corruptions conditions. The predefined signal corruption conditions comprise, for example, (i) digital data encoded in the one or more signals maintaining a same binary value for two or more consecutive clock cycles (to indicate intersymbol interference); and (ii) a predefined minimum number of aggressor data edges in digital data encoded in the one or more signals, and a corresponding predefined number of victim data edges in the digital data encoded in the one or more signals, wherein the victim edges are moving in an opposite direction to the aggressor data edges (to indicate simultaneous switching outputs).