Transmitter Circuit Timing for ISI-Compensated Analog Output
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Solution Overview
Problem
Existing transmitter devices face challenges in generating analog signals that effectively compensate for inter-symbol interference (ISI) in transmission paths, leading to deteriorated waveforms that worsen signal reception in receiver devices.
Innovation Solution
The transmitter device employs a feed forward equalizer (FFE) with a digital processing circuit and delay circuits to generate differential signals, using multiplexers and drivers to create composite analog signals that compensate for ISI by adding a waveform between symbol intervals, ensuring compatibility with receiver devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transmitter devices generate analog signals for transmission, then signal transmission is achieved, but inter-symbol interference (ISI) occurs causing waveform deterioration and worsened signal reception
Solution Approach 1:
The transmitter device preemptively generates a compensation signal that anticipates and counteracts the inter-symbol interference before it degrades the main signal. The FFE calculates the expected ISI based on previous symbols and adds a compensation waveform to the current symbol, preventing waveform deterioration before it occurs during transmission.
Solution Approach 2:
The invention converts the harmful inter-symbol interference into a beneficial compensation signal. By analyzing the characteristics of ISI and generating an opposite-phase compensation waveform, the system transforms the detrimental effect into a protective mechanism that actively cancels out the interference, thereby improving signal reception quality.
2Reliability
If feed forward equalizer (FFE) is used to compensate for ISI, then signal reception quality improves, but device complexity increases due to additional circuits
Solution Approach 1:
The FFE circuit is integrated into the existing transmitter structure, merging the equalization function with the signal generation pathway. The compensation signal is combined with the main signal through a summing junction that is part of the existing driver circuitry, avoiding the need for completely separate equalization hardware and reducing overall system complexity.
Solution Approach 2:
The delay circuits and multiplexers used in the FFE are designed to serve multiple functions: they not only generate the compensation signal for ISI but also manage clock timing and coordinate the operation of different transmitter components. This multi-functionality reduces the total number of dedicated circuits needed, thereby limiting the increase in device complexity.
Data Source
AI summary
According to one embodiment, a transmitter device includes: a digital processing circuit generating n-phase first and second digital signals, the second digital signal shifted from the first digital signal by a first phase; a delay circuit generating an n-phase second clock signal shifted from an n-phase first clock signal by a second phase being 0 or more and being the first phase or less; a first multiplexer converting the first digital signal into a single-phase third digital signal based on the first clock signal; a second multiplexer converting the second digital signal into a single-phase fourth digital signal shifted from the third digital signal by a sum of the first phase and the second phase based on the second clock signal; and a first driver outputting a composite signal of first and second analog signals based on the third and fourth digital signals.