Transmitting Device Buffer Control for 5G Latency

The patent segments the buffer into multiple independent buffer regions, each associated with different logical channels and having different discard timer settings. This allows low-latency data to be stored in buffer regions with shorter discard timers while high-reliability data can use longer discard timers, thus resolving the contradiction between transmission reliability and latency by applying different buffering strategies to different data types.

The patent applies different quality characteristics to different parts of the buffer by configuring separate discard timers for different logical channels. Each logical channel can have its own discard timer value tailored to its specific latency requirements, enabling the system to optimize both reliability and latency for different data streams simultaneously within the same buffer structure.

The patent implements dynamic discard timer management where the discard timer for each logical channel can be independently configured and adjusted based on the specific requirements of that logical channel. This dynamic configuration allows the system to maintain flexibility in transmission control while preventing head-of-line blocking by ensuring that low-latency data is not held back by longer timers intended for other data types.

By segmenting the buffer into multiple regions with different discard timer configurations, the system allows each segment to operate with its own timing characteristics. This segmentation enables the system to maintain overall transmission control flexibility while allowing specific segments to prioritize speed for low-latency applications, thus resolving the contradiction between flexibility and transmission speed.

The patent segments the buffer management at the logical channel level rather than aggregating all channels into single buffer groups. This segmentation allows each logical channel to have its own buffer region and discard timer configuration, maintaining fine-grained control over latency requirements while still providing a structured management framework that does not excessively increase device complexity.

The patent applies local quality control by allowing each logical channel within a logical channel group to have its own discard timer setting tailored to its specific latency requirements. This approach maintains the complexity-reducing benefit of logical channel grouping while preventing the aggregation from causing latency violations, as each channel can be optimized locally for its timing needs.