Transmon Qubit Vacuum Gap Capacitor Design

The patent transitions from a planar interdigitated finger structure to a three-dimensional stacked capacitor configuration. Multiple capacitor plates are arranged in vertical layers separated by dielectric materials, effectively utilizing the third dimension (height) to increase capacitance without expanding the lateral footprint. This dimensional transition allows achieving high capacitance values while maintaining a compact device area.

The patent employs thin-film dielectric layers with controlled thickness and material properties to minimize dielectric losses while maintaining the necessary capacitance. By using high-quality thin dielectric films with low loss tangents and optimizing their thickness, the design reduces the volume of dielectric material exposed to electric fields, thereby minimizing dielectric losses and extending coherence time while still achieving the required charge noise immunity through adequate capacitance.

The patent utilizes composite capacitor structures combining multiple dielectric materials with different properties in a stacked configuration. By stacking dielectric layers with varying permittivities and loss characteristics, the design achieves high effective capacitance in a compact volume. This composite approach allows maintaining charge noise sensitivity while reducing the lateral dimensions of the qubit, enabling better integration density.