Transparent Clocking in 400G Cross Connect Systems
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Solution Overview
Problem
Collapsing multiple clock domains in cross connect systems, particularly in FPGA implementations with limited clock resources, is challenging due to the need for separate clock resources for each ingress-egress port combination, especially in high-data-rate applications like 400 G cross connect systems with 10 G resolution.
Innovation Solution
A transparent clocking system generates synthesized clock signals adjusted to match recovered clock signals from ingress ports, eliminating the need for direct synchronization and multiplexing, using a local oscillator and parts per million detectors to fine-tune clock rates, allowing multiple clock domains to be handled with limited resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple recovered clock signals are multiplexed to clock egress ports, then input and output clock rates can be matched, but the number of clock resources required increases significantly
Solution Approach 1:
Multiple recovered clock signals are multiplexed onto a single physical clock line that serves multiple egress ports. The clock selector circuit combines multiple clock inputs (CLK0-CLK3) into a shared clock resource, reducing the total number of clock lines required while maintaining the ability to match input and output clock rates for different port combinations.
Solution Approach 2:
A clock selector circuit dynamically selects which recovered clock signal to use for each egress port based on the active ingress-egress connection. The selector can switch between multiple clock sources (CLK0-CLK3) to match the clock rate of the connected ingress port, enabling flexible clock rate adaptation without dedicated clock lines for each port pair.
2Ease of operation
If separate clock resources are allocated for each ingress-egress port combination, then clock synchronization is simplified, but the physical footprint and component count increase
Solution Approach 1:
Each egress port is configured to accept multiple clock sources through the clock selector circuit, making it universally compatible with different ingress ports regardless of their specific clock rates. The shared clock infrastructure serves multiple functions: clocking data for different port combinations, adapting to various clock domains, and reducing overall system complexity.
Solution Approach 2:
The clock selector circuit acts as an intermediary between the multiple recovered clock signals and the egress ports. It receives multiple clock inputs, selects the appropriate clock based on the active connection, and provides it to the egress port, thereby simplifying the synchronization process without requiring dedicated clock resources for each port pair.
3Productivity
If 40 different clock domains are collapsed in a 400 G cross connect system, then high-data-rate transmission is enabled, but FPGA clock resources become insufficient
Solution Approach 1:
The 40 different clock domains are segmented into a smaller number of representative clock signals (CLK0-CLK3) that are recovered from sample ingress ports. Instead of handling all 40 clock domains independently, the system segments them into manageable groups that can be multiplexed and selected, reducing the FPGA clock resource burden while maintaining support for high-data-rate transmissions.
Solution Approach 2:
The system changes the parameter of clock signal representation by recovering clock signals at different phases or rates and using a selector to switch between them. This parameter transformation allows the FPGA to handle multiple clock domains through a reduced set of physical clock resources, enabling 400 G data transmission without requiring proportional clock resource expansion.
Data Source
AI summary
A cross connect apparatus or system with transparent clocking, consistent with embodiments described herein, connects a selected source or ingress port to a selected destination or egress port and clocks data out of the selected egress port using a synthesized clock that is adjusted to match a recovered clock from the selected ingress port. A transparent clocking system may generate the synthesized clock signal with adjustments in response to a parts per million (PPM) rate detected for the associated recovered clock signal provided by the selected ingress port. The cross connect system with transparent clocking may be a 400 G cross connect system with 10 G resolution. The cross connect system with transparent clocking may be used in optical transport network (OTN) applications, for example, to provide an aggregator and/or an add-drop multiplexer (ADM) or to provide a reconfigurable optical add-drop multiplexer (ROADM) upgrade to a higher data rate.