Transparent Conductive Layer Stacking for High Definition TFT
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Solution Overview
Problem
Current TFT substrates for liquid crystal display devices, particularly in FFS mode, face challenges in achieving high definition and transmittance due to limitations in electrode design and material usage, such as reduced aperture ratio and transmittance compared to IPS mode, and the need for higher performance with broader applications.
Innovation Solution
A semiconductor device with a thin-film transistor structure that includes a gate line layer, source line layer, and a specific configuration of transparent conductive layers with a dielectric layer, where the second transparent conductive layer overlaps with the first transparent conductive layer and the dielectric layer, forming a contact portion that reduces size and increases overlap with the gate line layer, enhancing aperture ratio and transmittance, and utilizing an oxide semiconductor layer for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If transparent electrodes are used in FFS mode liquid crystal display devices, then aperture ratio and transmittance are increased, but definition is reduced
Solution Approach 1:
The patent transitions from a planar electrode structure to a three-dimensional stacked structure with multiple transparent conductive layers (first transparent conductive layer 15 and second transparent conductive layer 19a) separated by a dielectric layer 17. This vertical stacking allows the contact portion to overlap with the gate line layer when viewed from the front, effectively hiding the contact structure from the viewing angle and maintaining high definition while preserving the transmittance benefits of transparent electrodes
Solution Approach 2:
The patent divides the electrode structure into multiple segments: the first transparent conductive layer 15, the dielectric layer 17, and the second transparent conductive layer 19a. This segmentation allows each layer to perform its specific function while collectively achieving the dual goals of high transmittance and high definition through their stacked arrangement
2Area of stationary object
If oxide semiconductor TFT is used, then transistor size is reduced and transmittance is increased, but pixel capacitance charging efficiency becomes insufficient
Solution Approach 1:
The patent adds a vertical dimension to the capacitor structure by stacking the first transparent conductive layer 15, dielectric layer 17, and second transparent conductive layer 19a. This three-dimensional capacitor configuration increases the capacitance value without expanding the planar area, thereby maintaining the small transistor size enabled by oxide semiconductor TFT while providing sufficient pixel capacitance charging capacity
Solution Approach 2:
The stacked transparent conductive layers serve multiple functions: they form the pixel electrode structure for light transmission, create the capacitor structure for charge storage, and enable the contact portion to overlap with the gate line layer for high definition. This multi-functionality resolves the contradiction between small size and sufficient capacitance
Data Source
AI summary
This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole. The second transparent conductive layer contacts with the drain electrode in the first contact hole to form a contact portion (105), which at least partially overlaps with a gate line layer when viewed along a normal to a substrate.