Transparent Host Memory Buffer for DRAM-Less Storage
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Solution Overview
Problem
As storage capacity increases, the size of the L2P table also grows, requiring larger DRAM for storage, which is expensive. Additionally, DRAM-less controllers lack sufficient internal RAM to cache all L2P tables, leading to inefficiencies in mapping table access.
Innovation Solution
The implementation of a transparent host memory buffer (HMB) allows the host device to access the HMB for mapping table data, enabling the host device to send read commands with embedded mapping table information and signature verification, thereby reducing the need for direct HMB access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger DRAM is used to store L2P tables, then mapping table storage capacity is improved, but cost increases
Solution Approach 1:
The L2P table is extracted from the controller's internal DRAM and stored externally in the host device's memory buffer (HMB). This extraction eliminates the need for large amounts of expensive DRAM in the controller while maintaining full mapping table storage capacity, as the host device provides the external memory resource.
Solution Approach 2:
The host device's memory buffer is utilized for dual purposes: serving as general host memory and simultaneously storing the L2P table for the data storage device. This multi-functionality allows the same memory resource to fulfill multiple roles, eliminating the need for dedicated DRAM in the controller.
2Ease of manufacture
If DRAM-less controller is used, then cost is reduced, but mapping table access speed deteriorates
Solution Approach 1:
The host device pre-loads the L2P table into its memory buffer before the data storage device needs to access it. By having the mapping table ready in advance in the HMB, the controller can quickly retrieve mapping information without needing its own DRAM cache, thus maintaining fast access speed while using a DRAM-less architecture.
Solution Approach 2:
The host device's memory buffer acts as an intermediary between the controller and the persistent storage media. It provides a fast-access layer for L2P table data, mediating the access speed requirement without requiring the controller to have expensive DRAM, thereby enabling DRAM-less design while maintaining performance.
3Speed
If controller caches L2P tables in internal RAM, then mapping table access speed is improved, but device complexity increases
Solution Approach 1:
The L2P table caching function is extracted from the controller and relocated to the host device's memory buffer. This extraction simplifies the controller's architecture by removing the need for internal DRAM and associated cache management logic, while the host device's existing memory infrastructure handles the caching function.
Solution Approach 2:
The host device serves itself by using its own memory buffer to store and provide L2P table data to the controller. This self-service approach eliminates the need for the controller to have dedicated caching resources, reducing controller complexity while maintaining fast access through the host's memory system.
Data Source
AI summary
The present disclosure generally relates to utilizing a transparent host memory buffer (HMB) where the host device is granted access to the HMB to obtain data from a mapping table. The data storage device stores the mapping table in HMB and then allows the host device to view the mapping table and retrieve information. The host device sends a command to the data storage device that includes not only a read command, but also mapping table info specific to the read command. Additionally, an indication of the mapping table version from where the information is also provided. The data storage device, upon receiving the command, confirms the version of the information is the most recent version and then, if confirmed, utilizes the mapping information provided with the command. In so doing, accessing the HMB after receiving the command will not be necessary.