Transparent MBIST for In-System Memory Testing Without Data Loss
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Solution Overview
Problem
Existing in-system memory testing techniques face challenges such as time constraints, interference with normal operations, and the need to preserve memory content, especially in safety-critical applications like automotive and IoT systems, where in-field faults due to process variation and aging phenomena are significant.
Innovation Solution
The implementation of memory built-in self-test (MBIST) circuitry that segments memory tests into subsets, storing and restoring memory contents using internal registers during idle periods, allowing flexible scheduling and efficient handling of interrupt commands, while using physical data patterns for fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional in-system memory testing is performed, then fault detection capability is improved, but normal memory operations are disrupted and memory content is lost
Solution Approach 1:
The patent segments the memory into multiple banks and divides test operations into phases, allowing different banks to be tested at different times while others remain operational. This segmentation enables partial testing without complete system disruption, resolving the contradiction between fault detection and operational continuity.
Solution Approach 2:
The patent creates copies of memory content in buffer memory during testing phases. By copying data to buffers before testing and restoring from buffers after testing, the original memory content is preserved even while testing occurs, allowing fault detection without permanent data loss or operational disruption.
2Measurement precision
If comprehensive memory testing is performed, then fault detection accuracy is improved, but testing time exceeds available idle periods
Solution Approach 1:
The memory testing is segmented into multiple phases (first phase, second phase, third phase) that can be executed during different idle periods. Each phase tests specific portions or aspects of the memory, allowing comprehensive testing over extended periods rather than requiring one continuous long test that would exceed available idle time.
Solution Approach 2:
The patent implements periodic testing where different memory banks are tested in alternating periods. While one bank undergoes comprehensive testing during an idle period, other banks remain operational. This periodic rotation allows thorough testing of all memory without requiring all testing to occur within a single idle period constraint.
3Ease of operation
If memory testing is performed during idle periods, then interference with normal operations is reduced, but fault detection completeness is compromised
Solution Approach 1:
The patent employs periodic testing across multiple idle periods, systematically testing different memory banks in rotation. This ensures that while each individual test occurs during limited idle time with minimal interference, the cumulative effect of periodic testing across all banks achieves complete fault detection coverage.
Solution Approach 2:
The patent performs preliminary data copying to buffer memory before testing begins. This preliminary action preserves the original data, allowing the memory to be tested thoroughly during idle periods without risking data loss. The preliminary copying enables more aggressive testing protocols that would otherwise be too risky, thereby improving fault detection completeness without increasing operational interference.
Data Source
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AI summary
A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In- system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.